Deep copy in System Verilog

SystemVerilog
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1

I have doubt in the following snippet which is related to deep copy.


// Packet is a class with properties addr and data.
// It also has instance of another class ar
  function packet copy(); //Here copy is just name of the function
    copy = new(); // where is the copy handle declared? 
    // How are we allocating memory to a fucntion declaration?
    // The function definition is not complete yet
    // How can we use the same name here...? Why does the compiler give no error ?
    copy.addr = this.addr;
    copy.data = this.data;
    copy.ar   = ar.copy;//calling copy function of tr
    return copy;
  endfunction

COPY Method 2

  function packet copy_1();
    packet curr_copy;
    curr_copy= new();
    curr_copy.addr = this.addr;
    curr_copy.data = this.data;
    curr_copy.ar   = ar.copy;
    return curr_copy;
  endfunction

What is the difference between method 1 and method 2 ?
Is there any recursion concept involved in method 1?

2

From the LRM:
13.4.1 Return values and void functions
The function definition shall implicitly declare a variable, internal to the function, with the same name as the function. This variable has the same type as the function return value. Function return values can be specified in two ways, either by using a return statement or by assigning a value to the internal variable with the same name as the function.