Topics tagged SystemVerilog

Topic	Replies	Views	Activity
SVA - check signal value not changing during the entire clock cycle SystemVerilog SystemVerilog , SVA	8	80	May 18, 2024
Locators for packed arrays SystemVerilog SystemVerilog	3	19	May 16, 2024
Wr_en is high for one extra clock cycle even if fifo full is asserted SystemVerilog SystemVerilog	1	18	May 16, 2024
Ignoring array of bins in cross SystemVerilog SystemVerilog , cross-coverage , SystemVerilog-FunctionalCoverage	10	1933	May 15, 2024
Why assertion failure at 15ns SystemVerilog SystemVerilog , assertion	1	31	May 14, 2024
Understanding the performance impact of SVA construct SystemVerilog SystemVerilog , system-verilog-assertion-SVA	5	1109	May 14, 2024
Multiple clocks in SVA assertion SystemVerilog SystemVerilog , assertion , SVA	1	39	May 13, 2024
System verilog randomization SystemVerilog SystemVerilog , constraint-randomization , randomization	1	44	May 12, 2024
About new tech learning UVM SystemVerilog , UVM	0	43	May 10, 2024
Randomize dynamic array with unique values SystemVerilog SystemVerilog , dynamic-arrays , dynamic-array-constraint , systemverilog-constraint , uvm-dynamicarray	8	1358	May 9, 2024
Confusion about threads SystemVerilog SystemVerilog	2	44	May 8, 2024
Initializing a Register File SystemVerilog SystemVerilog , initialization , register-file	1	30	May 7, 2024
SVA: Package for dynamic and range delays and repeats SystemVerilog SystemVerilog , dynamic-delays-dynamic-repeats	10	22776	May 7, 2024
System verilog interview questions SystemVerilog SystemVerilog	2	72	May 7, 2024
Discrepancy on legality of the consequent SystemVerilog SystemVerilog , SVA , system-verilog-assertion-SVA , SVA-Assertion	9	108	May 6, 2024
Randomization of beats SystemVerilog SystemVerilog , UVM	2	43	May 6, 2024
Using goto repetition SystemVerilog SystemVerilog , Using-goto-repetition	4	312	May 4, 2024
Smart way to bundle up multiple RTL signals when passing to monitor SystemVerilog SystemVerilog , UVM-monitor	1	47	May 2, 2024
Randc variable randomization inside top sequence class SystemVerilog SystemVerilog , constraint-randomization , randomization , randc-usage-constraint , systemverilog-constraint	3	52	May 1, 2024
How to cover unsigned int UVM SystemVerilog , UVM , Coverage	1	70	April 30, 2024
SystemVerilog Hiearchial Reference to UUT Internal Signal? SystemVerilog SystemVerilog	2	43	April 30, 2024
System verilog inheritance for sequences SystemVerilog SystemVerilog	4	51	April 30, 2024
Using sequence method triggered within Sampled value functions SystemVerilog SystemVerilog , assertion , SVA , SVA-Assertion	5	102	April 27, 2024
How can you set order for the execution of initial begin blocks without using event or wait statements? SystemVerilog SystemVerilog	1	42	April 27, 2024
How text macro affect inside and outside pkg? SystemVerilog SystemVerilog , compilation-macro	2	34	April 27, 2024
Performance problem SystemVerilog SystemVerilog	3	70	April 24, 2024
Constraint Randomization Interview Question SystemVerilog SystemVerilog	17	4338	April 24, 2024
Vopt-13412) Virtual methods of an object or built-in method are not allowed in event control expressions SystemVerilog SystemVerilog	1	43	April 23, 2024
Arr.sum() - constraint SystemVerilog SystemVerilog , systemverilog-constraint	1	94	April 23, 2024
What is the general difference between static and dynamic events in SystemVerilog? SystemVerilog SystemVerilog	3	935	April 23, 2024