System verilog randomization

SystemVerilog
, ,
1

I have a class with two random variables, such as addr and data. to implement randc function for one variable i have used below code.

class c1;

    //queue to store generated variables
    bit [1:0] q [$];

    rand bit [1:0] addr;

    //set the membership
    //y should not be generated before
    constraint c {
        !(addr inside {q});
    }


    function void post_randomize();
        q.push_front(addr);

        //if the size equals to the number of all combinations, clear the queue
        if(q.size()==4)
            q.delete();

    endfunction

endclass

But if i want implement the randc on variable data, so how can i do, should i use one more queue… if that is the case, if i have 10 varibles should i use 10 queues?

Can some one help me with this?

2

You need to explain why you cannot use randc. Otherwise, yes, you will need a separate queue for each variable. And if there are other constraints on these variables, you will need to figure out when to delete the queue and start over.