System verilog interview questions

SystemVerilog
1

there is a dut which has serial input signal with each bit driven for 1ns.i.e bit 0 takes 1 ns and bit 1 takes 1ns. and there is no clock . and the dut recognizes 32’A5A5A5A5 pattern and gives output 1 when it recognizes that specific pattern. could you please let me know how I can pass information from bits 0 to bit 15 to the model so that it also recognizes the pattern and checks whether dut is aseerting 1 or 0 upon recognizing the pattern. I would not like use the monitor to get the information for 1ns and pass it to the model.

Thanks in Advance

2

If your DUT is not synchronized with a clock it does not mean your testbench does also not use clock. Simply define a clock signal in your testbench which prvides the data as required in your driver.

1 Like
3

thanks chr_sue for the clarifications. Could you please clarify whether in this case can i pass the data to model from driver ?( assuming monitor is not having the clock so dont want to use monitor).or from the sequence to model?