Using goto repetition

SystemVerilog
,
1

Hi,
Consider the following SVA:


  sequence checkAck;
   !( $rose(read) && (readID == localID)) throughout ($rose(readAck)&&(readAckID == localID ))[->1] ;
  endsequence
  property  checkRead ;
     int  localID ;
     $rose(read),localID = readID ) |=> checkAck;
  endproperty

  ap_p:assert property( @(posedge clk) CheckRead );

Goto repetition is used with expression : ( $rose(readAck) && (readAckID == localID ) )

However when I write:


  sequence checkAck;
   !( $rose(read) && (readID == localID)) throughout ($rose(readAck) ##0(readAckID == localID ))[->1] ; // Changed RHS sequence from '&&' to '##0'
  endsequence

I observe compilation error.

[Q1]Why is sequence_expression invalid for goto repetition ?

As I have seen examples where goto repetition is used with sequence methods ‘.triggered’ and ‘.matched’.
[Q2]I am wondering what are all legal ways to use goto repetition ?

[Q3] Do the same rules apply for Nonconsecutive repetition as well ?

2

In reply to MICRO_91:

The sequence repetition operators are poorly named. They, in fact, only handle repetitions of boolean expressions.

The sequence methods triggered() and matched() return boolean values

1 Like
3

In reply to dave_59:
Thanks Dave.

They, in fact, only handle repetitions of boolean expressions.

Hence $rose/$fell/$stable/$changed are also legal for sequence repetition operators ( as they return boolean values 1’b0/1’b1.

4

Hi Dave,
LRM 16.9.2 states

In particular, goto repetition and nonconsecutive repetition cannot be applied to a Boolean expression to which a sequence match item has been attached. 

For example, the following is a legal sequence expression:
(b[->1], v = e)[*2]
but the following is illegal:
(b, v = e)[->2]                        //  boolean_expr used as sequence_expr

Since sequence_match_item aren’t blocking , why do we have this restriction ?

5

The reason, by the SVA committee, could have been for efficiency