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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
    • Languages & Standards

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      • Functional Safety
      • Design & Verification Languages
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    • Techniques & Tools

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      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
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  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
    • Universal Verification Methodology (UVM)

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      • UVMF - One Bite at a Time
    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification
    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters
    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking
    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.
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  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
    • Implementation Patterns

      • Environment Patterns
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      • Analysis Patterns
      • All Implementation Patterns
    • Specification Patterns

      • Occurrence Property Patterns
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    • Pattern Resources

      • Start Here - Patterns Library Overview
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  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
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      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook
    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines
    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
    • Upcoming & Featured Events

      • Creating an Optimal Safety Architecture  - February 9th
      • The ABC of Formal Verification - February 11th
      • Events Calendar
    • On Demand Seminars

      • I'm Excited About Formal...
      • Visualizer Coverage
      • Formal-based ‘X’ Verification
      • 2020 Functional Verification Study
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  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
    • Blog & News

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SystemVerilog
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4886 questions in SystemVerilog

  • TITLE
    SOLVED
    REPLIES
    VIEWS
    POSTED
    UPDATED
  • Solve...before does not work in this specific scenario
    2  
    66  
    6 hours 7 min ago
    by dannyg  
    2 hours 58 min ago
    by dave_59  
  • SVA to check frequency and duty cycle with +/- 5% error
    3  
    141  
    2 days 3 hours ago
    by foxtrot  
    3 hours 37 min ago
    by foxtrot  
  • distributed weightage constraint
    9  
    23,656  
    7 years 4 months ago
    by Hani John Poly  
    5 hours 28 min ago
    by dave_59  
  • Confusion with disable fork?
    4  
    122  
    1 day 9 hours ago
    by Lokesh402  
    17 hours 48 min ago
    by yourcheers  
  • randomization inside value list
    1  
    60  
    1 day 12 hours ago
    by alexkidd84  
    1 day 9 hours ago
    by cgales  
  • the difference between clocking block event and its actual clocking event
    1  
    74  
    2 days 15 hours ago
    by Dosia  
    1 day 10 hours ago
    by cgales  
  • Endless assertion, any other way to rewrite it?
    1  
    63  
    2 days 6 hours ago
    by jcastillo  
    1 day 17 hours ago
    by ben@SystemVerilog.us  
  • SYSTEM TASK EXAMPLES
    2  
    119  
    2 days 8 hours ago
    by Shivansh Bhardwaj  
    1 day 18 hours ago
    by Shivansh Bhardwaj  
  • Assertion for counting clock cycles during reset pulse
    8  
    309  
    5 days 10 hours ago
    by spoiled rabbit  
    2 days 21 hours ago
    by ben@SystemVerilog.us  
  • Is there a way to change ModelSim's default radix in code or command line?
    1  
    60  
    3 days 26 min ago
    by BrianHG  
    2 days 23 hours ago
    by ben@SystemVerilog.us  
  • @always position
    2  
    101  
    1 week 10 hours ago
    by likhith bommu  
    3 days 8 hours ago
    by likhith bommu  
  • Ternary operator vs if else
    7  
    7,485  
    2 years 11 months ago
    by manjush_pv  
    3 days 13 hours ago
    by eliasdkh  
  • Capture data only on rising falling signal
    2  
    94  
    5 days 9 hours ago
    by trg  
    4 days 12 hours ago
    by trg  
  • How do I write a binary dump file of an array in my testbench.
    6  
    149  
    5 days 20 hours ago
    by BrianHG  
    4 days 21 hours ago
    by BrianHG  
  • Parametrized Assertion
    4  
    149  
    6 days 57 min ago
    by tejasakulu  
    5 days 6 hours ago
    by ben@SystemVerilog.us  
  • Which HDL has probability of consuming more simulation time between SV and Verilog?
    5  
    144  
    1 week 17 hours ago
    by bachan21  
    6 days 16 min ago
    by dave_59  
  • SDF Delay is much larger than clock then it disabled DLL
    1  
    64  
    1 week 15 hours ago
    by jcungduoc  
    1 week 7 hours ago
    by jcraft  
  • assertion to check number of clock pulses
    12  
    255  
    1 week 6 days ago
    by gv_bing  
    1 week 1 day ago
    by ben@SystemVerilog.us  
  • Dynamic Array in System Verilog?
    1  
    104  
    1 week 1 day ago
    by Arun_Rajha  
    1 week 1 day ago
    by ben@SystemVerilog.us  
  • #delay is not working as expected in system verilog class (timescale issue)
    5  
    3,534  
    2 years 2 weeks ago
    by kranthi445  
    2 years 2 weeks ago
    by kranthi445  

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13,439 Questions

40,278 Replies

69,288 Users

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