Deferred assertions

SystemVerilog
, ,
1

If I want to check on a signal after asynchronous reset with (assert final) then why I have to use combinational always block Why I can’t use for example: always@(negedge reset)

2

/* If I want to check on a signal after asynchronous reset with (assert final)
then why I have to use combinational always block
Why I can’t use for example: always@(negedge reset) */
WHo says you have to use combinational always block .
Options I see:

 always@(negedge reset) am_reset_sig: assert final(sig==0);

 always_comb 
   if($fell(reset, @(posedge clk))) am2_reset_sig: assert final(sig==0);

Ben Cohen
Ben@systemverilog.us
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