Calling a function with class argument inside a constraint

SystemVerilog
1 
class reg_block extends uvm_reg_block;
rand custom_reg1 reg1[1:24];
rand custom_reg2 reg2;

constraint c1
{
    (func(reg1)) -> (reg2.field1.value == 0);
};

function bit func(custom_reg1 regs[1:24]);
    int count = 0;
    foreach(regs[i])
        if (regs[i].field2.value != 2'b10)
            return 1;
    return 0;
endfunction
endclass

I just want to make sure that if at least one of the 24 reg1 field2 is not 2’b10, reg2.field1 should be 0.

Error-[IVCB-INTARG] Non integral function argument
…/uvm_env/***.sv, 489
***, “this.reg1”
The argument ‘this.reg1’ is not an integral expression or array.
Change the type of the expression or remove it from the constraint.

How can I achieve this?

2

I guess the only way is to declare a rand integral array and use it’s type as argument instead and let it be equal to the reg1[i].field2.value inside the constraint…

3

You can use one of the array reduction methods

constraint c1
{
    reg1.or(regs) with (regs.field2.value != 2'b10)  -> (reg2.field1.value == 0);
};