Could nonblocking(<=) used in always_comb?

SystemVerilog
1

could nonblocking(<=) used in always_comb?

  //aw
   always_comb
     begin
        axi_awaddr                         <= 0;
        case (current_state)
          WR_REG_VDMACR  :      axi_awaddr <= 'h30;
          WR_REG_MM2S_HSIZE   : axi_awaddr <= 'hA4;
          WR_REG_MM2S_VSIZE   : axi_awaddr <= 'hA0;
          default : axi_awaddr             <= 0;
        endcase
     end

what is the difference of nonblocking and blocking in always_comb ?

2

Nonblocking assignments should never be used in combinational logic unless assignment propagation delays are needed to make some asynchronous or analog logic work.

Nonblocking assignments in combinational logic may cause extra signal rippling and if used in the clock path may cause race conditions.