Is there any clue to implement a systemverilog like constraint-solver in python

SystemVerilog
1

Hi, everyone.

Is there any way to implement a systemverilog like constraint-solver in python? I’m working on building a random instruction generator which is built by systemverilog before, and it costs a lot of time to debug-and-rebuild the generator, so I’m wondering if python can do this kind of job.

Thanks

2

See pyvsc as one example which tries to mimic SV’s features and API. It’s open source so don’t expect perfection, but I found it useful on a previous project for replicating block UVM testbench constraints in a different environment.