Generate, genvar

SystemVerilog
1

I have some code in tb top.

    assign my_if[0].ck  =  CK0; 
    assign my_if[1].ck  =  CK1; 
    assign my_if[100].ck =  CK100;

How do I wrap the above code using generate/endgenerate, genvar?
The square bracket variable worked for me, but it did not work for CK*

i.e. The following does not work for CK*
generate
for (genvar z=0; z<=100; z=z+1) begin : foo
assign my_if[z].ck = CKz;
end
endgenerate

Thanks!

2

There is no way to iterate over identifier names within the SystemVerilog language. You can:

  • convert CK0...CK100 into an array
  • generate the SV code using an editor/perl/python script and include it.
3

Use arrays. If not, use macro.