For below Assert property i'm getting offending error, can anyone help me with this

SystemVerilog
1 
property chk_in_st(int);
@(posedge assert_clk) disable iff (!rst_n)
  !hold_ack_n & $rose (int_flag[int])|-> in_st throughout(int_flag[int]##[0:$] hold_ack_n);
endproperty

F0:assert property(chk_in_st(0)) else assert_flag = 1;
:
: 
F45: assert property(chk_in_st(45)) else assert_flag = 1;
2

The argument in the property does not accept a data type. You have to pass a variable.

3

Hi chr_sue-san, actually int having 48 bit width so for all 0 to 45 i’m checking interrupt property.
but when i’m checking at 46 and 47 position getting this offending error.

4

Please format your code making your code easier for others to read. I have done that for you. SystemVerilog code does not always render correctly without it.

We are confused because int is a reserved keyword for a datatype. I think you meant to use some name like i.

You also need to explain what an “offending error” means. Is it a compiler error message or an assertion error. Please show us, and show us declarations for all variables. Better would be a minimal, complete reproducible examples

5

Okay. I got your point. Actually I’m writing at reserved bit so that’s the reason I’m seeing offending error. It’s resolved.

6

Can i access the global variable which is declared in the assertion module in the property and endproperty ,if yes then can i access the config class variables in the property and endproperty.

7

This would have been better to be asked as a new question as it is unrelated to the original post.

You can access static variables (globals) from a property, but not non-static class members.

8

Thank you Dave it’s working.