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UVM scoreboard interview question
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|
4
|
658
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February 12, 2026
|
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Calling parent function via super is calling child class function
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4
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69
|
February 12, 2026
|
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Virtual Sequence
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1
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82
|
February 11, 2026
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Read values are wrong in UART Verification
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9
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79
|
February 9, 2026
|
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Package not bound
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2
|
41
|
February 9, 2026
|
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SVA sampling of always( a ##1 b[->1] )
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6
|
72
|
February 8, 2026
|
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Uvm reset sequence on all the regsioters
|
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3
|
68
|
February 4, 2026
|
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How are registers supposed to deal with resets in UVM 2020?
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6
|
77
|
February 3, 2026
|
|
Vending Machine in System Verilog
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2
|
251
|
February 2, 2026
|
|
Scoreboard evaluating before monitor updates in SystemVerilog testbench (DFF)
|
|
1
|
82
|
January 29, 2026
|
|
Constraint Randomization Interview Question
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22
|
5698
|
January 25, 2026
|
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Evaluation of following Embedded Concurrent assertion
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0
|
62
|
January 18, 2026
|
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Interview question on constraint
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24
|
12219
|
January 20, 2026
|
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Assertion question :-
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9
|
578
|
January 18, 2026
|
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Calling a Task at the end of run_phase
|
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3
|
115
|
January 17, 2026
|
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Full_case parallel_case concrete explanation needed
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2
|
89
|
January 12, 2026
|
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Constraint Pattern problem
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5
|
188
|
January 10, 2026
|
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SystemVerilog constraint: unique addr across array of structs without auxiliary array
|
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3
|
129
|
January 9, 2026
|
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How SV handles the execution of functions
|
|
1
|
75
|
January 9, 2026
|
|
Requesting clarity on constraint solving
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|
2
|
109
|
January 7, 2026
|
|
AHB Lite protocol Verification
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|
2
|
710
|
January 7, 2026
|
|
Working of uvm_cmdline_processor::get_arg_matches
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|
3
|
84
|
January 6, 2026
|
|
Query on generating rand 2D array with sum of set bits equal to specific value and bits must be connected to each other
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4
|
142
|
January 5, 2026
|
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Assertion error
|
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3
|
83
|
January 5, 2026
|
|
Using interface in testbench and for modules connection
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|
1
|
65
|
January 5, 2026
|
|
Uvm_hdl_read gives Incorrect value
|
|
3
|
140
|
January 4, 2026
|
|
Weighted constraints not working
|
|
3
|
97
|
January 2, 2026
|
|
Assertion calculation after reset
|
|
0
|
58
|
January 2, 2026
|
|
Sequence which admits : No match v/s Hard Zero
|
|
8
|
440
|
December 27, 2023
|
|
System verilog Assertion
|
|
4
|
154
|
January 1, 2026
|