Verification Academy

Topic	Replies	Views	Activity
Continuous assignment between two inout SystemVerilog inout , continuous-assignment	3	42	November 19, 2025
Redefine a SV interface port direction in a modport SystemVerilog	2	75	November 19, 2025
What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules? UVM OVM , SystemVerilog , UVM , Coverage	0	64	November 17, 2025
Wait_for_state() in a static module doesn't work as expected UVM UVM-phase-methods , UVM_PHASE , phase , Cookbook-Phasing , UVM-phases , Related-to-UVM-phases , phasing , Phasing-within-a-static-entity	10	134	November 16, 2025
UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses UVM SystemVerilog , UVM , uvm-register-model	2	69	November 13, 2025
Individual field access causes extra reads/writes? UVM SystemVerilog , UVM , uvm-register-model	5	45	November 12, 2025
Resume simulation when any 2 threads out of 3 get completed within fork-join_any SystemVerilog SystemVerilog , fork-join_any	9	4222	November 12, 2025
Verifying synchronours fifo SystemVerilog	3	84	November 11, 2025
Question regarding followed by operator in SVA (#-# and #=# SystemVerilog SystemVerilog , SVA , SVA-Assertion	0	58	November 11, 2025
System verilog constraint help SystemVerilog SystemVerilog , constraint-randomization	2	114	November 11, 2025
UVM RAL: How to execute register access without updating mirrored value? UVM UVM-RAL-UVM	1	71	November 8, 2025
VHDL Code Coverage - Generate Statements Coverage Coverage	2	40	November 6, 2025
Code debug help UVM	2	82	November 5, 2025
Need help understanding formal verification of asynchronous FIFO SystemVerilog assertion , System-Verilog , SVA , Formal-Verification	0	69	November 3, 2025
Chained Implications in SVA SystemVerilog SystemVerilog , Coverage , assertion , SVA , axi , AHB	0	57	November 3, 2025
Why only ##1 (single delay operator) used in the case of multiple clock sequences? SystemVerilog SystemVerilog , assertion	2	674	November 3, 2025
Vertical re-use (from block to sub-system/chip level) UVM UVM , reuse	5	3341	November 2, 2025
Migrating from IP to sub-system level UVM	2	78	November 2, 2025
restricting sequence as long as one variable is asserted SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	4	74	November 2, 2025
Default value of enumarated varaible is first value of enum SystemVerilog	4	60	November 1, 2025
difference b/w nexttime and ##1 SystemVerilog assertion	1	57	October 31, 2025
Why ref bit and int doesnt Work in sampling but int andref bit Does Coverage	0	38	October 31, 2025
Paper: Understanding SVA Degeneracy SystemVerilog SystemVerilog , SystemVerilog-SVA	9	600	October 29, 2025
In my design, I have an assign statement like assign var = (a == b) ? 1 : 0;. During simulation, var takes both values 1 and 0 as expected, but in Questa code coverage, this statement is still shown as not covered. Why is this happening? Coverage Coverage , questasim	2	38	October 29, 2025
SVA with multiple Implication operators SystemVerilog	0	49	October 29, 2025
Why uvm_object_registry is called as lightweight proxy? UVM UVM	1	63	October 28, 2025
Function inside constraint SystemVerilog	1	86	October 28, 2025
UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure UVM UVM	5	102	October 27, 2025
is $fell(sig_a) true when sig_a from x to 0? SystemVerilog assertion , SVA	1	74	October 27, 2025
Question regarding latch behaviour SystemVerilog	1	62	October 27, 2025