I am currently implementing an SPI VIP in UVM. I am a bit confused with the functionality of the master monitor and slave monitor. The architecture is shown below. Kindly tell me the difference in the functionality of master and slave monitor so that I can implement it myself. I have implemented master and slave driver as follows. (For now I have muted slave sequencer block, i.e slave agent will have only monitor and driver)
Master Driver:
Make the slave select down and then send an opcode to slave driver.
If the opcode is write , based on the # of bitcounts we need to transfer the data via MOSI. If read then only send the bitcount # of clock cycles to the slave.
Slave driver:
Receive the slave select, opcode details. If write then create a memory and store the bits in it.
If read then send the bitcount amount of data to master using MISO.
The ideal solution is to create a single VIP solution. It would contain a driver which can act as either a master or slave (based upon the agent configuration) along with a monitor.
Let’s say there are BFMs for master driver and slave driver. Now using the same “monitor plan” mentioned below - can I use it for master monitor and slave monitor ? Because I don’t see any functional difference between the master and slave monitors, only the signal perspectives at each end(I mean master and slave). This itself can be used for scoreboard checking. What do you say?
Monitor plan:
when the slave select goes down, then for 8 clock cycles get the opcode from MOSI, based on the opcode if read then get MISO bits and send to scoreboard.If write then note down all the data sent to slave and send that packet to scoreboard.
The monitor doesn’t care about opcodes or reads or writes. All the monitor should do is detect when SS goes low, record the bytes sent on MISO and MOSI, and detect SS going high.
This data will be sent out of the agent as a SPI transaction and the scoreboard will determine if the DUT functionality is correct. You only need one monitor for this functionality.
