Connection using modports with different signals

SystemVerilog
, ,
1

Dear Forum,

Is it allowed to connect two modules using SV interface modports with different signals :

interface chip_bus ();
   logic [31 :0] address;
   logic [63:0]  data;
   logic [63:0]  req;
  // The two modports use different signals
  modport master (input  address, output req);
  modport slave  (output address, input  data);
endinterface

// primary
module primary   (chip_bus.master pins); 
endmodule

// secondary
module secondary (chip_bus.slave pins);
endmodule

// top
module top ();
   chip_bus  bus  (); 
   secondary i2   (bus) ;
   primary   il   (bus); 
endmodule

If yes how this shall be connected

Thanks
Jamal

2

Yes, this is perfectly valid. Are you having a specific issue?

3

This means only 'address‘ is connected ?

4

I’m not sure what you mean.

In the module primary, you have access to address and req. In the module secondary, you have access to address and data.

5

yes, I mean in this case primary.address and secondary.address are connected, but primary.req and secondary.data not connected ?

6

An interface is a group of signals. A modport allows you to connect a sub-set (or all) of these signals with directionality as a group instead of each individual signal. The signals still remain independent, so req and data are not connected.
The module ‘primary’ has access to req, and ‘secondary’ has access to data, but they are not interconnected.

1 Like
7

Hi @jamal , I suppose what you want to do is connecting data and req in the interface. Then, you can use modport expressions for that purpose.

interface chip_bus ();
   logic [31 :0] address;
   logic [63:0]  signal;
  // The two modports use different signals
  modport master (input  address, output .req (signal));
  modport slave  (output address, input  .data(signal));
endinterface

The following also works.

interface chip_bus ();
   logic [31 :0] address;
   logic [63:0]  data;
  // The two modports use different signals
  modport master (input  address, output .req(data));
  modport slave  (output address, input data);
endinterface

The signal names pins.req and pins.data are referred in primary and secondary respectively.
You can look up the term “modport expressions” of SystemVerilog interface.