Time does not strictly flow forward

SystemVerilog
1

First to execute during a time slot is the Active region, where design events run. These include your traditional RTL and gate code plus the clock generator. The second region is the Observed region, where SystemVerilog Assertions are evaluated. Following that is the Reactive region where the testbench code in a program executes. Note that time does not strictly fl ow forwards - events in the Observed and Reactive regions can trigger further design events in the Active region in the current cycle. Last is the Postponed region, which samples signals at the end of the time slot, in the readonly period, after design activity has completed. - SystemVerilog for verification by chris spear & Greg Tumbush

module tb_top;

  logic       clk;
  logic [2:0] a;
  
  always @(a)begin
    $display("A is changed : %0d at time %3t",a,$time);
  end
  
  program testbench;

    initial begin
      #1 a = 1;  
      $display("REACTIVE : Driving a=1 at time %3t", $time);
       
      #1 a = 2;
      $display("REACTIVE : Driving a=2  at time %3t", $time);
      
      #1 a = 3;
      $display("REACTIVE : Driving a=3  at time %3t", $time);
      
      #1 a = 4;
      $display("REACTIVE : Driving a=4  at time %3t", $time);
      
      #10 $finish();
    end
  endprogram

endmodule

This is my sample code to understand the above statements. But I want a better view on this line “Time doesn’t strictly flow forward” . with a sample code.

2

I believe that it means that when all events in the active region are completed, that the time doesn’t automatically advance. Following regions may result in additional events being added to the active region in the same time stamp, so the scheduler will go back and execute the new events added.

This loop will occur until all events in that time slot are completed, and then time will advance.