Time does not strictly flow forward

SystemVerilog
1

First to execute during a time slot is the Active region, where design events run. These include your traditional RTL and gate code plus the clock generator. The second region is the Observed region, where SystemVerilog Assertions are evaluated. Following that is the Reactive region where the testbench code in a program executes. Note that time does not strictly fl ow forwards - events in the Observed and Reactive regions can trigger further design events in the Active region in the current cycle. Last is the Postponed region, which samples signals at the end of the time slot, in the readonly period, after design activity has completed. - SystemVerilog for verification by chris spear & Greg Tumbush

module tb_top;

  logic       clk;
  logic [2:0] a;
  
  always @(a)begin
    $display("A is changed : %0d at time %3t",a,$time);
  end
  
  program testbench;

    initial begin
      #1 a = 1;  
      $display("REACTIVE : Driving a=1 at time %3t", $time);
       
      #1 a = 2;
      $display("REACTIVE : Driving a=2  at time %3t", $time);
      
      #1 a = 3;
      $display("REACTIVE : Driving a=3  at time %3t", $time);
      
      #1 a = 4;
      $display("REACTIVE : Driving a=4  at time %3t", $time);
      
      #10 $finish();
    end
  endprogram

endmodule

This is my sample code to understand the above statements. But I want a better view on this line “Time doesn’t strictly flow forward” . with a sample code.

2

I believe that it means that when all events in the active region are completed, that the time doesn’t automatically advance. Following regions may result in additional events being added to the active region in the same time stamp, so the scheduler will go back and execute the new events added.

This loop will occur until all events in that time slot are completed, and then time will advance.

3

@cgales Thanks for the response. Yeah. I understand that. Can you provide a bit clearer code to understand this?

@dave_59 what is your take on this?

5

I would avoid using program blocks; they make SystemVerilog unnecessarily complex.

module top;
  
  int A,B;
  bit clk;
  
  always @(posedge clk) begin
    A =  A + 1;
    B <= B + 1;
    $display("Time: %3d A: %3d B: %3d", $time, A, B);
  end;
  
  initial begin
    
    $display("Within Active region - does not consume time");
    repeat (10) clk = ! clk;
    
    $display("Active/inactive loop - does not consume time");
    repeat (10) #0 clk = ! clk;
    
    clk <= ! clk;
    $display("Active/NBA loop - does not consume time");
    repeat (10) @clk  clk <= ! clk;
    
    $display("Active/Active Time consuming loop");
    repeat (10) #1 clk = ! clk;
    
  end
endmodule

Output:

Within Active region - does not consume time
Active/inactive loop - does not consume time
Time:   0 A:   1 B:   0
Time:   0 A:   2 B:   0
Time:   0 A:   3 B:   0
Time:   0 A:   4 B:   0
Time:   0 A:   5 B:   0
Active/NBA loop - does not consume time
Time:   0 A:   6 B:   1
Time:   0 A:   7 B:   2
Time:   0 A:   8 B:   3
Time:   0 A:   9 B:   4
Time:   0 A:  10 B:   5
Active/Next-Active Time consuming loop
Time:   0 A:  11 B:   6
Time:   2 A:  12 B:   7
Time:   4 A:  13 B:   8
Time:   6 A:  14 B:   9
Time:   8 A:  15 B:  10