Difference between always and always_comb

SystemVerilog
1

Is there any functional difference between following two blocks, cuz I am seeing behavioural difference when I am using one than the other


always_comb begin
	   rd_ptr_next = rd_ptr;
	   if(rd_en) begin
		  rd_ptr_next = rd_ptr + 1;
	   end
end

 // and

always @(rd_en, rd_ptr) begin
	   rd_ptr_next = rd_ptr;
	   if(rd_en) begin
		  rd_ptr_next = rd_ptr + 1;
	   end
end
2

It would help greatly to explain the differences you are seeing.

always @(...) suffers from time 0 race conditions that always_comb avoids by ensuring that the latter triggers at time 0 regardless of whether or not it sees any event triggers.

1 Like
3 

module tb_top;
logic a = 1;
logic b = 0;
logic y;

initial begin
$monitor(“TIME: %3t y=%0d”, $time,y);  //   y = 0
end

always_comb begin
y = a & b;
end
endmodule

//---------------------------

module tb_top;
  logic a = 1;
  logic b = 0;
  logic y;

  initial begin
    $monitor("TIME: %3t y=%0d", $time,y);    // y = x
  end

  always @(*) begin
    y = a & b;
  end
endmodule

@Aman551 If we put $display to check the difference there will be none. by the time $display executes our always blocks have not executed yet.

But @dave_59 why I cannot spot the difference with the below code?

module sample_design(input logic x, output logic y);
  always_comb begin
    y = x;
  end
endmodule : sample_design


module tb_top();
  logic a = 1'b1;
  logic b;
  sample_design dut(.x(a),.y(b));
  
  initial begin
    $monitor($time,"b : %0b",b);
  end
  
  
endmodule: tb_top
4

@Thobiyas, your first example would be a race condition between the execution of the $display (assuming you replaced the $monitor) and the execution of the always_comb block. In your second example, the always @(*) block never executes. In both examples, the initialization of the variables a and b took place before the execution of any initial or always blocks.

In your third example, even though the initialization of the variables happens before the execution of any initial or always blocks, the propagation of those variable values through the module ports x and y are now in a race with the always blocks. However, most tools will execute the always blocks first.

1 Like