Difference between always and always_comb

SystemVerilog
1

Is there any functional difference between following two blocks, cuz I am seeing behavioural difference when I am using one than the other


always_comb begin
	   rd_ptr_next = rd_ptr;
	   if(rd_en) begin
		  rd_ptr_next = rd_ptr + 1;
	   end
end

 // and

always @(rd_en, rd_ptr) begin
	   rd_ptr_next = rd_ptr;
	   if(rd_en) begin
		  rd_ptr_next = rd_ptr + 1;
	   end
end
2

It would help greatly to explain the differences you are seeing.

always @(...) suffers from time 0 race conditions that always_comb avoids by ensuring that the latter triggers at time 0 regardless of whether or not it sees any event triggers.