Is it possible to use function in assertion but variable widths of the function variables are parameters?

SystemVerilog
1

I want to have reusable assertion checkers with package of functions but i want to use parameters in both depending on the project. Is there a way to do it and then in TB i could just bind and pass parameters to “test_module“?
Below is kind of example of what i want to have.

package func_pkg;
   function bit[parameter_a : 0] func_a(bit[parameter_b : 0] in_a);
      return in_a[parametar_a:0];
   endfunction
endpackage

module test_module#(parameter x, parameter y)(input bit clk)
property check_me;
   @(posedge clk)  
   func_a#(x,y) |-> 1';
endproperty
assert property(check_me)
endmodule
2 
package func_pkg;
  function bit do_xor(input bit x, input bit y);
    return x ^ y;
endfunction
endpackage

module test_module#(parameter x=0, parameter y=1)(input bit clk);
  bit   a; 
property p_check_me;
  bit v; 
   @(posedge clk)  
   (1, v=do_xor(x,y)) ##0 v |-> a; 
endproperty : p_check_me
ap_check_me: assert property(p_check_me);
endmodule
```
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