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"Building a theater set is not unlike what we do as verification engineers. It involves modeling the "real world," often at a higher level of abstraction, and it has hard deadlines."
—Tom Fitzpatrick
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Building a theater set is not unlike what we do as verification engineers. It involves modeling the "real world," often at a higher level of abstraction, and it has hard deadlines. "The show must go on," after all. Productivity is also key because all of us building the set are volunteers. We reuse set pieces whenever we can, whether it's something we built for a past production or something we borrowed from a neighboring group. And we often have to deal with shifting requirements when the director changes his mind about something during rehearsals. Oh, and it also involves tools – lots of tools. However, there is one important way in which set construction is different from verification. Those of us building theater sets know our work only has to stay up for two weeks and that no one in the audience is going to see it from closer than thirty feet away. In contrast, all engineers know the chips they verify must work a lot longer under much closer scrutiny.
One of the most challenging things about doing musical theater is the audition. It's your one chance to make the right impression on the director who decides which performers will be in the show. For engineers, our audition is the interview, and our first article today, "Interviewing a Verification Engineer," by Akiva Michelson of Ace Verification, will walk you through this process. As an interviewer, I hope you'll find this article useful to help you identify the best candidate for your team. And as a candidate, it'll show you what you ought to prepare for.
A well-built set piece that can be used over and over again is truly a treasure. Similarly, a well-built configurable Verification IP component (VIP) can have a huge impact on your productivity. In "Maximum Productivity with Verification IP," you'll see how Mentor VIP provides a self-contained piece of your verification environment that includes everything you need to ensure that your design correctly implements a standard protocol, such as PCIe.
Part of the magic of set construction is that the set isn't really complete until it is painted and the lighting is set. The paint and the lights work together to emphasize certain aspects of the set and to focus the audience's attention where the director wants it. Our next article, "Power Up Hardware/Software Verification Productivity," shows how our inFact intelligent testbench automation tool lets you specify your stimulus – in this case, your power control scenarios – at a higher level of abstraction that can then be targeted either to sequences in UVM or to software running on your embedded processor. The underlying inFact engine will handle the coordination of both hardware- and softwarebased stimuli, covering everything the way paint and lights cover a set.
While it's great to use software-based stimulus to verify hardware, it's also necessary to verify the software itself in the context of the hardware on which it will run. In "Noninvasive Software Verification Using the Vista Virtual Platform" we'll see how our Vista Virtual Platform tool lets you instrument your software in a transparent manner to enable coverage, profiling and other analysis of your target software in simulation without affecting the target behavior.
In our Partners' Corner, we have a trio of articles from users who will share their experiences using different Mentor Graphics tools on their projects. In "QVM: Enabling Organized, Predictable and Faster Verification Closure," our friends at SmartPlay Technologies show how they use Questa's Verification Manager (QVM) to turn the huge amounts of simulation data generated throughout a project into useful information to provide their customers with a well-managed verification flow. In "Verifying High Speed Peripheral IPs," you'll see how our friends at Mobiveil take advantage of Questa CoverCheck and Questa Clock- Domain Crossing (CDC) verification to be able to deliver "correct by construction for configurability" IP cores to their customers. Lastly, in "Confidence in the Face of the Unknown: X-state Verification," our friends at MediaTek discuss how formal X-checking capabilities in Questa can identify situations where X-propagation in simulation could mask problems that would show up in silicon.
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