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  1. An Up-sized DAC Issue Takes the Stage

    Building a theater set is not unlike what we do as verification engineers. It involves modeling the "real world," often at a higher level of abstraction, and it has hard deadlines. "The show must go on," after all. Productivity is also key because all of us building the set are volunteers. We reuse set pieces whenever we can, whether it's something we built for a past production or something we borrowed from a neighboring group. And we often have to deal with shifting requirements when the director changes his mind about something during rehearsals.

    Oh, and it also involves tools – lots of tools. However, there is one important way in which set construction is different from verification. Those of us building theater sets know our work only has to stay up for two weeks and that no one in the audience is going to see it from closer than thirty feet away. In contrast, all engineers know the chips they verify must work a lot longer under much closer scrutiny.

    One of the most challenging things about doing musical theater is the audition. It's your one chance to make the right impression on the director who decides which performers will be in the show. For engineers, our audition is the interview, and our first article today, "Interviewing a Verification Engineer," by Akiva Michelson of Ace Verification, will walk you through this process. As an interviewer, I hope you'll find this article useful to help you identify the best candidate for your team. And as a candidate, it'll show you what you ought to prepare for.

    While it's great to use software-based stimulus to verify hardware, it's also necessary to verify the software itself in the context of the hardware on which it will run. In "Non-invasive Software Verification Using the Vista Virtual Platform" we'll see how our Vista Virtual Platform tool lets you instrument your software in a transparent manner to enable coverage, profiling and other analysis of your target software in simulation without affecting the target behavior.

    In our Partners' Corner, we have a trio of articles from users who will share their experiences using different Mentor Graphics tools on their projects. In "QVM: Enabling Organized, Predictable and Faster Verification Closure," our friends at SmartPlay Technologies show how they use Questa's Verification Manager (QVM) to turn the huge amounts of simulation data generated throughout a project into useful information to provide their customers with a well-managed verification flow.

    In "Verifying High Speed Peripheral IPs," you'll see how our friends at Mobiveil take advantage of Questa CoverCheck and Questa Clock- Domain Crossing (CDC) verification to be able to deliver "correct by construction for configurability" IP cores to their customers. Lastly, in "Confidence in the Face of the Unknown: X-state Verification," our friends at MediaTek discuss how formal X-checking capabilities in Questa can identify situations where X-propagation in simulation could mask problems that would show up in silicon.

    In our Consultants' Corner, we have three more articles in which consultants share their knowledge and experience in developing verification infrastructure that you may find useful on your own projects. In "Making it Easy to Deploy the UVM," our friends at Frobas GmbH show how the regular structure of a UVM testbench enables them to automate the creation of UVM environments, including some sequences and tests. Once the environment is up and running, they show the benefits of using Questa Verification Manager on a regular basis to help monitor verification progress.

    In "NoC Generic Scoreboard VIP," the engineers at Test and Verification Solutions explain how they developed a UVM Network-on-Chip (NoC) scoreboard component. The article discusses many of the issues you'll need to think about when developing a verification environment involving multiple transaction types and protocols – useful information whether you use this component directly or not. We round out the Consultants' Corner with "Flexible UVM Components: Configuring Bus Functional Models," from our friends at Ensilica. In this article, which builds on "Polymorphic Interfaces: An Alternative for SystemVerilog Interfaces" from our November, 2011 issue, you'll see how to use wrapper classes and a few simple rules to implement a bus functional model (BFM) as a SystemVerilog interface that appears to the test like it's a UVM component.

    We conclude this special issue with two papers from last February's DVCon. The first, "Monitors, Monitors Everywhere – Who Is Monitoring the Monitors?" by my colleagues Rich Edelman and Raghu Ardeishar, won a Best Poster award for the conference. When you read it and learn about the myriad of issues that must be considered when designing monitors and scoreboards, you'll see why. Last but not least, "The Need for Speed: Understanding Design Factors That Make Multi-Core Parallel Simulations Efficient," you'll learn how best to take advantage of Questa's new Multi-Core Multi-Computer (MC2) technology to maximize your run-time performance.

    So, there you have it – our Texas-sized issue of Verification Horizons. If you're at DAC this week, stop by and say hi. I have plenty of videos of Megan's performances on my phone and I'll be happy to show them off.

    Respectfully submitted,

    Tom Fitzpatrick - Editor, Verification Horizons

    Tom Fitzpatrick
    Editor, Verification Horizons

June 2013