A New Stimulus Model for CPU Instruction Sets
Verifying that a specific implementation of a processor is fully compliant with the specification is a difficult task. Due to the very large total stimuli space it is difficult, if not impossible, to ensure that every architectural and microarchitectural feature has been exercised.
Advanced Testbench Configuration with Resources
Building robust, reusable testbenches means the testbench elements must be configurable. At its essence, configuring a testbench is a matter of populating a database with name/value pairs and providing a means for testbench objects to access that database.
Intelligent Testbench Automation - Now a Reality, No Longer Just a Promise
Using a current benchmark as the basis for the content, this article describes a Questa/inFact solution in which a small engineering team was able to fully verify an SOC IP module design, in less time and with fewer resources, than with the best their current constrained random test solution.
Closing the Loop in Testbench Automation
Existing testbench techniques offer various benefits. However, once a testbench is initiated, it runs open-loop, generating results and then reporting them to an engineer. In turn, the engineer analyzes the results, makes some modifications to the system, and runs it again - and then repeats the process.