Improving Performance and Verification of a System Through an Intelligent Testbench
The need for intelligent verification is the outcome of a two decade long pre-silicon verification process. Intelligent testbench automation, which is a supplement of intelligent verification, is a step closer towards achieving more confidence in design with minimal engineering effort. Applications today demand diverse functionality, which results in complex to very complex designs. Pre-silicon verification for first-pass success using current verification approaches is just not enough.
A New Stimulus Model for CPU Instruction Sets
In this article we present an alternative approach, using a portable, environment independent model of the stimulus. The CPU instruction set, and various contexts in which the instructions appear, are all modeled by a graph.
Is Intelligent Testbench Automation For You?
There have been multiple technical papers demonstrating successful verification applications and panel sessions comparing the merits to both Constrained Random Testing (CRT) and Directed Testing (DT) methods.
Automated Generation of Functional Coverage Metrics for Input Stimulus
Verification teams are always under pressure to meet their project schedules, while at the same time the consequences of not adequately verifying the design can be severe.
Targeting Internal-State Scenarios in an Uncertain World
The challenges inherent in verifying today's complex designs are widely understood. Just identifying and exercising all the operating modes of one of today's complex designs can be challenging.
Hiding the Guts
We verification test bench designers are happy sausage makers, merrily turning out complex and powerful verification environments. To us, object-oriented programming environments not only greatly enhance our productivity, but they make us feel smarter.