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Simulation-Based Techniques

Simulation-Based Techniques

This topic area focuses on simulation-based techniques, ranging from stimulus generation, coverage modeling, and correctness checking. Building a contemporary testbench using UVM is also covered in this topic area.

Simulation-Based Techniques Courses

Power Aware Verification

Power Aware Verification Course | Subject Matter Expert - Erich Marschner | Simulation-Based Techniques Topic

This course introduces the IEEE Std 1801 Unified Power Format (UPF) for specification of active power management architectures and covers the use of UPF in simulation-based power aware verification.

Intelligent Testbench Automation (iTBA)

Intelligent Testbench Automation Course | Subject Matter Expert - Mark Olen | Simulaton-Based Techniques Topic

This course provides a complete introduction to Intelligent Testbench Automation (iTBA), showing how you can achieve your coverage goals >10X faster.

Evolving FPGA Verification Capabilities

Evolving FPGA Verification Capabilities Course | Subject Matter Expert - Ray Salemi | Simulation-Based Techniques Topic

This course introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.

Assertion-Based Verification

Assertion-Based Verification (ABV) Course | Subject Matter Expert - Harry Foster | Simulation-Based Techniques Topic

UPDATED COURSE!
This course introduces a set of steps for advancing an organization’s assertion-based-verification (ABV) skills, infrastructure, and metrics.

Simulation-Based Techniques Resources

Is Intelligent Testbench Automation For You?

There have been multiple technical papers demonstrating successful verification applications and panel sessions comparing the merits to both Constrained Random Testing (CRT) and Directed Testing (DT) methods.
Horizons Article

Automated Generation of Functional Coverage Metrics for Input Stimulus

Verification teams are always under pressure to meet their project schedules, while at the same time the consequences of not adequately verifying the design can be severe.
Horizons Article

Targeting Internal-State Scenarios in an Uncertain World

The challenges inherent in verifying today's complex designs are widely understood. Just identifying and exercising all the operating modes of one of today's complex designs can be challenging.
Horizons Article

Hiding the Guts

We verification test bench designers are happy sausage makers, merrily turning out complex and powerful verification environments. To us, object-oriented programming environments not only greatly enhance our productivity, but they make us feel smarter.
Horizons Article

Mentor Graphics New Questa Platform Functionality Boosts Productivity across the Verification Spectrum

The Questa functional verification platform contains an integrated set of leading-edge technologies that address the major verification challenges faced by today’s complex SoC, ASIC, and FPGA designs.
Press Release

Intelligent Testbench Automation - Catching on Fast

While intelligent testbench automation is still reasonably new when measured in EDA years, this graph-based verification technology is being adopted by more and more verification teams every day.
Blog Post

Instant Replay for Debugging SoC Level Simulations

Multi-core designs present a whole new level of verification challenges. Achieving functional coverage of your IP blocks at the RTL level has become merely a pre-requisite now – as they say “necessary but not sufficient”.
Blog Post

Advanced Testbench Configuration with Resources

Building robust, reusable testbenches means the testbench elements must be configurable. At its essence, configuring a testbench is a matter of populating a database with name/value pairs and providing a means for testbench objects to access that database.
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Intelligent Testbench Automation - Now a Reality, No Longer Just a Promise

Using a current benchmark as the basis for the content, this article describes a Questa/inFact solution in which a small engineering team was able to fully verify an SOC IP module design, in less time and with fewer resources, than with the best their current constrained random test solution.
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Closing the Loop in Testbench Automation

Existing testbench techniques offer various benefits. However, once a testbench is initiated, it runs open-loop, generating results and then reporting them to an engineer. In turn, the engineer analyzes the results, makes some modifications to the system, and runs it again - and then repeats the process.
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Accelerating Coverage Closure with Intelligent Testbench Automation

This archived web seminar shows how the Questa inFact Intelligent Testbench Automation solution generates stimulus according to the user s functional coverage goals, eliminating redundant stimulus and efficiently targeting corner cases. The result is 10x to 100x faster functional coverage closure.
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Verifying Complex SoC Designs with Questa Codelink

This archived web seminar shows how Questa Codelink helps verification engineers reduce the time spent finding design errors and debugging them, at the SoC level, in both simulation and emulation environments.
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