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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
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      • UVM Forum

    • SystemVerilog Forum

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      • SystemVerilog Forum

    • Coverage Forum

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      • Coverage Forum

    • Additional Forums

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      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • DVClub | Milpitas, CA
      • Emulation User Forum 2020 | Bengaluru & Hyderabad
      • DVCon 2020 | San Jose, CA
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • All On-Demand Seminars

    • Recording Archive

      • DAC 2019 Session Recordings
      • User2User Silicon Valley 2019
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • SystemVerilog Randomization
      • Instructor-led Training

    • Mentor Learning Center

      • Introduction to Visualizer
      • Mastering Questa Learning Path
      • ModelSim/Questa Tcl/TK Overview
      • Stimulus Optimization with inFact
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - December 2019
      • Verification Horizons - June 2019
      • Verification Horizons - February 2019
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • Questa® inFact
      • Functional Verification Library
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  • Simulation-Based Techniques

Simulation-Based Techniques

Simulation-Based Techniques

This topic area focuses on simulation-based techniques, ranging from stimulus generation, coverage modeling, and correctness checking. Building a contemporary testbench using UVM is also covered in this topic area.

Simulation-Based Techniques Courses

Power Aware Verification

Power Aware Verification Course | Subject Matter Expert - Erich Marschner | Simulation-Based Techniques Topic

This course introduces the IEEE Std 1801 Unified Power Format (UPF) for specification of active power management architectures and covers the use of UPF in simulation-based power aware verification.

Assertion-Based Verification

Assertion-Based Verification (ABV) Course | Subject Matter Expert - Harry Foster | Simulation-Based Techniques Topic

This course introduces a set of steps for advancing an organization’s assertion-based-verification (ABV) skills, infrastructure, and metrics.

An Introduction to Unit Testing with SVUnit

Introduction to Unit Testing with SVUnit Course | Subject Matter Expert - Neil Johnson, XtremeEDA | Simulation-Based Techniques Topic

SVUnit is an open-source test framework for ASIC and FPGA developers writing Verilog/SystemVerilog code. SVUnit is the only SystemVerilog test framework suited for both design and verification engineers.

Questa® Simulation Resources

  • Articles
  • White Papers
  • On-Demand
  • Seminars
  • Training
  • Product Information

Featured Simulation-Based Techniques Verification Horizons Articles

  • Effective Elements Lists and the Transitive Nature of UPF Commands
  • A New Approach to Low-Power Verification: Power Aware Apps
  • Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs
  • Part I: Power Aware Static Verification - From Power Intent to Microarchitectural Checks of Low-Power Designs
  • A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs
  • PA GLS: The Power Aware Gate-level Simulation
  • Understanding the UPF Power Domain and Domain Boundary
  • Artifacts of Custom Checkers in Questa® Power Aware Dynamic Simulation
  • Automation and Reuse in RISC-V Verification Flow
  • Complementing Functional Verification Through the Use of Available Timing Information
  • How to Get the Maximum Out of Your Assertion and Coverage Based Verification Methodology
  • First Time Unit Testing Experience Report with SVUnit
  • The Verification Academy Patterns Library
  • Reusable Verification Framework
  • Power Aware Libraries: Standardization and Requirements for Questa® Power Aware
  • Successive Refinement: A Methodology for Incremental Specification of Power Intent
  • PowerAware RTL Verification of USB 3.0 IPs
  • Taming Power Aware Bugs with Questa®
  • The Evolution of UPF: What's Next?
  • Evolution of UPF: Getting Better All the Time

Featured Simulation-Based Techniques White Papers

  • A New Approach to Low-Power Verification: Power Aware Apps
  • Moving Beyond Assertions: An Innovative Approach to Low-Power Checking Using UPF Tcl Apps
  • Efficient Modeling Styles and Methodology for Gate-Level Design Verification
  • The Big Brain Theory: Visualizing SoC Design and Verification Data
  • Boosting Regression Throughput by Reusing Setup Phase Simulation
  • The Need For Speed: Understanding Design Factors That Make Multi-Core Parallel Simulations Efficient
  • Traffic Profiling and Performance Instrumentation For On-Chip Interconnects
  • Effective Elements List and Transitive Natures of UPF Commands
  • Low Power Apps: Shaping the Future of Low Power Verification
  • UPF Information Model: The Future of Low-Power Verification Today
  • Low Power Coverage: The Missing Piece in Dynamic Simulation
  • Random Directed Low-Power Coverage Methodology: A Smart Approach to Power Aware Verification Closure
  • Free Yourself from the Tyranny of Power State Tables with Incrementally Refinable UPF
  • The Fundamental Power States for UPF Modeling and Power Aware Verification
  • Power Aware CDC Verification of Dynamic Frequency And Voltage Scaling (DVFS) Artifacts
  • Stepping into UPF 2.1 World: Easy Solution to Complex Power Aware Verification
  • Advanced Verification of Low Power Designs
  • To Retain or Not to Retain: How Do I Verify the State Elements of My Low Power Design?
  • Low Power Design and Verification Techniques

Featured Simulation-Based Techniques On-Demand Technical Sessions

  • Why Reset Domain Crossing Verification is an Emerging Requirement
  • Clock-Domain Crossing Analyses and Verification
  • Integrated Approach to Power Domain/Clock-Domain Crossing Checks
  • Breaking the Speed Limits on SoC Verification with the Questa® Flow
  • Navigating the Perfect Storm: New School Verification Solutions
  • New Low Power Verification Techniques
  • Building An Integrated Verification Flow
  • Power Aware Simplifies Parametric PA-SIM Regression
  • Debugging Trends, Challenges, and Novel Solutions
  • Advanced Verification for All: SV/UVM, UCIS, UPF Made Easy
  • Verification and Validation in the SoC Age
  • Add Unit Testing To Your Verification Tool Belt
  • Back to the Stone Ages for Advanced Verification
  • Verification Patterns: An Optimized Reusable Solution

Featured Simulation-Based Techniques Seminars

  • Low Power Verification Forums
  • Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips
  • Testbench Automation: How to Create a Complex Testbench in a Couple of Hours
  • New School Verification Technologies
  • Design & Verification in the SoC Era

ModelSim® / Questa® Core Advanced Topics

This learning path enables you to extend your knowledge of ModleSim/QuestaSim functionality and to efficiently analyze and debug HDL code.

  • ModelSim/Questa Tcl/TK Overview
  • ModelSim/Questa Code Coverage
  • ModelSim/Questa Language Support and Gate Level Simulations
  • ModelSim/Questa Finite State Machine Viewer
  • ModelSim/Questa Selected Debugging Topics

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Questa’s Core Simulation and Debug Engine

The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug and functional coverage capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF and UVM.

The Questa Advanced Simulator is the core simulation and debug engine of the Questa Verification Solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.

Learn more | Datasheet

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