I am trying to drive a module that is several layers down in my hierarchy. In synthesis, the module is created by a Block Design. For simulation, I’m replacing it with a model, but I’d like to be able to stimulate it from the testbench
For example:
module top(
//...
);
internal_module u1(
.spi_bus,
.axi_bus,
.gpio
);
//...
// other modules that use those signals
endmodule
module tb;
//...
top dut( .*);
//drive and read buses from dut.u1
endmodule
Is there a specific method that is preferred for accomplishing this? In the simplest way, this could be done by grabbing the signals individually (dut.u1.spi_bus), but the design has a lot of signals. If possible, I’d prefer to use tasks(dut.u1.send_spi(pkt)) so if I have to replace this module in another place, I don’t have to duplicate code.