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1901 Results

  • Overview to Improve AMS Quality

    This session introduces the challenges in improving Mixed-Signal Verification Quality.

  • AMS Design Configuration Schemes

    This session introduces a tool can be adapted in various topologies supporting the available methodologies with little or no impact on the design flow.

  • Mixing Languages

    This session defines the language choices available in a Mixed-Signal design structure and how each choice impacts the performance and quality of the process.

  • Design Topologies

    This session covers the 2 main design topologies: Analog-Centric Mixed-Signal Designs and Digital-Centric Mixed-Signal Designs

  • Design Methodologies

    This session covers the 2 main flows used in Mixed-Signal design environments: Bottom-Up Design Flow and Top-Down Design Flow.

  • Analog/Mixed-Signal Domain

    This session introduces the definition for Mixed-Signal domain and addresses the three main areas for AMS design: functionality, robustness and reliability.

  • Overview to AMS Configuration

    This session introduces the opposing powers in Design Methodologies and the concept of Mixed-Signal design environments. Challenges and techniques will also be covered.

  • Improve AMS Verification Performance

    This session introduces a tool that will help verify complex Mixed-Signal designs to reach the goal of successful first tape-out.

  • AMS Modeling Guidance

    This session attempts to offer some general guidelines in developing Models for the various Analog and Mixed-Signal domain.

  • Modeling Abstraction

    This session defines the language choices available in a Mixed-Signal design structure and how each choice impacts the performance and quality of the results.

  • AMS Engines

    This session covers the 2 main simulator technologies used in Mixed-Signal verification: AMS Simulation and Analog/Digital Co-Simulation.

  • Overview to Improve AMS Performance

    This session introduces the challenges in Mixed-Signal verification performance.

  • VHDL-2008 Overview

    This session is a brief overview of all the VHDL-2008 improvements.

  • Testbench Enhancements

    This session examines testbench enhancements and the value they deliver.

  • RTL Enhancements

    This session examines the RTL enhancements in VHDL-2008 and the value they deliver.

  • Operator Enhancements

    This session will discuss the value of the many new enhancements to the VHDL-2008 operators.

  • Package Type Enhancements

    The session explores the new packages and modifications to the packages as well as the value these updates deliver.

  • Fixed Point Package

    This session will explain the details of the new fixed point package.

  • Floating Point Package

    This session will explain the details of the new floating point package.

  • VHDL-2008 Why It Matters

    VHDL-2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed and floating point math packages.

  • Effectively Modeling and Analyzing Coverage

    In this session, we will outline a comprehensive coverage strategy that will help you implement effective functional coverage for your project. We will begin with a discussion of the different kinds of coverage and explain how to go from a functional specification to a coverage model, ensuring that your coverage code gives results that are easy to interpret.

  • Verification Horizons - Volume 8, Issue 3

    "For verification, productivity really comes down to being able to reliably determine if your chip will run correctly as efficiently as possible.”

  • UVM 1.1c Class Reference

    v1.1c The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.

  • More UVM Registers

    In this session, you will learn how to implement registers and score-boarding at the register layer.

  • Protocol Layering

    In this session, you will learn how to deconstruct sequence items and sequences across the protocol hierarchy and how to encapsulate each layer to preserve reuse.