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Register-Level Stimulus

Chapter - Mar 31, 2014 by Verification Methodology Team

Stimulus that accesses memory mapped registers should be made as abstract as possible.
Register Model & Structure

Chapter - Mar 31, 2014 by Verification Methodology Team

In order to be able to use the UVM register model effectively, it is important to have a mental model of how it is structured in order to be able to find your way around it.
Register Sequence Examples

Chapter - Mar 31, 2014 by Verification Methodology Team

To illustrate how the different register model access methods can be used from sequences to generate stimulus, this page contains a number of example sequences developed for stimulating the SPI master controller DUT.
Generating Register Models

Chapter - Mar 31, 2014 by Verification Methodology Team

A register model can be written by hand, following the pattern given for the SPI master example.
Integrating a UVM Register Model in a Testbench - Implementation

Chapter - Mar 31, 2014 by Verification Methodology Team

The integration process for the register model involves constructing it and placing handles to it inside the relevant configuration objects, and then creating the adaption layers.
Memory-Level Stimulus

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM register model also supports memory access. Memory regions within a DUT are represented by memory models which have a configured width and range and are placed at an offset defined in a register map
"Quirky" Registers

Chapter - Mar 31, 2014 by Verification Methodology Team

Quirky registers are just like any other register described using the register base class except for one thing.
Integrating a UVM Register Model in a Testbench - Overview

Chapter - Mar 31, 2014 by Verification Methodology Team

Within an UVM testbench a register model is used either as a means of looking up a mirror of the current DUT hardware state or as means of accessing the hardware via the front or back door and updating the register model database.
Register Model Coverage

Chapter - Mar 31, 2014 by Verification Methodology Team

Which covergroups get built within a register block object or a register object is determined by a local variable called m_has_cover.
The Sequence Library

Chapter - Mar 31, 2014 by Verification Methodology Team

UVM provides a class for randomly creating and running sequences. This class is called uvm_sequence_library.
Stopping a Sequence

Chapter - Mar 31, 2014 by Verification Methodology Team

Once started, sequences should not be stopped.
Virtual Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

A virtual sequence is a sequence which controls stimulus generation using several sequencers.
Slave Sequences (Responders)

Chapter - Mar 31, 2014 by Verification Methodology Team

A slave sequence is used with a driver that responds to events on an interface rather than initiating them. This type of functionality is usually referred to as a responder.
Wait for a Signal

Chapter - Mar 31, 2014 by Verification Methodology Team

In the general case, synchronizing to hardware events is taken care of in UVM testbenches by drivers (proxy & BFM) and monitors (proxy & BFM).
Interrupt Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

In hardware terms, an Interrupt is an event which triggers a new thread of processing.
Virtual Sequencers (Not Recommended)

Chapter - Mar 31, 2014 by Verification Methodology Team

A virtual sequence is a sequence which controls a stimulus generation process using several sequencers.
Command Line Processor

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM command line processor is used to interact with plusargs. Several plusargs are pre-defined and part of the UVM standard.
Transaction Methods

Chapter - Mar 31, 2014 by Verification Methodology Team

When working with data object classes derived from uvm_objects, including ones derived from uvm_transactions, uvm_sequence_items and uvm_sequences, there are a number of methods which are defined for common operations on the data objects properties.
End of Test

Chapter - Mar 31, 2014 by Verification Methodology Team

A UVM testbench, if is using the standard phasing, has a number of zero time phases to build and connect the testbench, then a number of time consuming phases, and finally a number of zero time cleanup phases.
UVM Driver

Chapter - Mar 30, 2014 by Verification Methodology Team

The UVM driver is responsible for communicating at the transaction level with the sequence via TLM communication with the sequencer and converting between the sequence_item on the transaction side and pin-level activity in communicating with the DUT via a virtual interface.
UVM Monitor

Chapter - Mar 30, 2014 by Verification Methodology Team

The first task of the analysis portion of the testbench is to monitor activity on the DUT. A Monitor, like a Driver, is a constituent of an agent.
UVM Factory

Chapter - Mar 27, 2014 by Verification Methodology Team

The purpose of the UVM factory is to enable an object of one type to be substituted with an object of a derived type without changing the testbench structure or even the testbench code.
Post-Run Phases

Chapter - Mar 27, 2014 by Verification Methodology Team

Many analysis components perform their analysis on an ongoing basis during the simulation run.
Backdoor Accesses

Chapter - Mar 27, 2014 by Verification Methodology Team

The UVM register model facilitates access to hardware registers in the DUT either through front door accesses or back door accesses.
Package Organization

Chapter - Mar 27, 2014 by Verification Methodology Team

UVM organizes all of its base classes into a SystemVerilog Package.

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Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

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Chapter - Mar 27, 2014 by Verification Methodology Team

Chapter - Mar 27, 2014 by Verification Methodology Team

Chapter - Mar 27, 2014 by Verification Methodology Team