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  • Transaction Methods

    When working with data object classes derived from uvm_objects, including ones derived from uvm_transactions, uvm_sequence_items and uvm_sequences, there are a number of methods which are defined for common operations on the data objects properties.

  • End of Test

    A UVM testbench, if is using the standard phasing, has a number of zero time phases to build and connect the testbench, then a number of time consuming phases, and finally a number of zero time cleanup phases.

  • UVM Driver

    The UVM driver is responsible for communicating at the transaction level with the sequence via TLM communication with the sequencer and converting between the sequence_item on the transaction side and pin-level activity in communicating with the DUT via a virtual interface.

  • UVM Monitor

    The first task of the analysis portion of the testbench is to monitor activity on the DUT. A Monitor, like a Driver, is a constituent of an agent.

  • UVM Factory

    The purpose of the UVM factory is to enable an object of one type to be substituted with an object of a derived type without changing the testbench structure or even the testbench code.

  • Post-Run Phases

    Many analysis components perform their analysis on an ongoing basis during the simulation run.

  • Backdoor Accesses

    The UVM register model facilitates access to hardware registers in the DUT either through front door accesses or back door accesses.

  • Package Organization

    UVM organizes all of its base classes into a SystemVerilog Package.

  • UVM Verification Component

    A UVC ( U VM V erification C omponent) is a Verification Component designed for use in UVM. It is a multi-faceted definition and has different layers of meaning in different contexts.

  • UVM Connect

    Learn about how to use UVM Connect to link UVM and SystemC using TLM.

  • UVMC Connections

    To communicate, verification components must agree on the data they are exchanging and the interface used to exchange that data.

  • UVMC Conversion

    Object transfer requires converters to translate between the two types when crossing the SC-SV language boundary.

  • UVMC Command API

    The UVM Connect Command API gives SystemC users access to key UVM features in SystemVerilog.

  • Questa Verification IP, More than just a BFM

    Today’s advanced UVM environments require more than a standard BFM to support environment reuse, randomized stimulus, generation of traffic scenarios, coverage collection, etc.

  • UART Example (.tgz)

    Most of the functional coverage can be derived from content of the registers which are used to control and monitor the behavior of the device. The register interface may also serve the data path. There may be scope for using assertions on signal interfaces.

  • Specification to Test Plan

    The goal in creating a coverage model spreadsheet or testplan is to capture a subset of the design intent and behavior that is targeted for functional coverage.

  • UART Example Test Plan

    As part of the verification planning process, a test plan should be drawn up to list all the design features to be tested and to help identify the type of functional coverage required to check that all the tests have been run for all conditions.

  • Executable Test Plan Format

    A testplan is a document which captures the important features of a design and how they will be verified.

  • Cookbook Code Examples

    The UVM Cookbook has a number of UVM code examples which are designed to help illustrate the various topics discussed. The link to each example also appears on the appropriate cookbook page.

  • UART Reference

    The Siemens EDA UART is a soft design IP core. It has been designed to be generally compatible with the industry standard 16550A UART, but there are a small number of differences.

  • Block Level Functional Coverage Example

    Block level functional verification can take full advantage of the the fact that all the block interfaces are exposed and can be stimulated separately with complete freedom.

  • Testplan to Functional Coverage

    Arriving at functional coverage closure is a process that starts with the functional specification for the design, which is analyzed to determine: What features need to be tested Under what conditions the features need to be tested What testbench infrastructure is required to drive and monitor the design's interfaces How the testbench will check that the features work

  • Bus Protocol Coverage

    A bus protocol defines how data is transferred between master and slave devices on the bus. The protocol specifies which signals are used to qualify when the master is making a request and when the slave is ready to respond to that request.

  • UART Example Covergroups

    The covergroup examples on this page are implementations of the functional coverage descriptions on the Block Level Functional Coverage Example page.

  • Requirements Writing Guidelines

    When creating a testplan , requirements to have a successful chip need to recorded in a useful, easy to digest manner. The following rules and guidelines will help to ensure this happens.