Search Results

Advanced Search

1772 Results

Dual Top Architecture

Chapter - Mar 31, 2014 by Verification Methodology Team

The dual top testbench architecture advocated throughout this cookbook enables platform portability - it is fundamental for testbench acceleration using emulation or some other hardware-assisted platform.
Parameterized Tests

Chapter - Mar 31, 2014 by Verification Methodology Team

SystemVerilog provides a number of ways to pass changeable values through different code structures. Some changeable values must be fixed at elaboration time and others can be changed at run-time after starting a simulation.
Testbench Build

Chapter - Mar 31, 2014 by Verification Methodology Team

The first phase of a UVM testbench is the build phase. During this phase, the uvm_component classes that make up the testbench hierarchy are constructed into objects.
Configuring Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

A frequently encountered scenario in sequence configuration involves setting up the agent's configuration object, encompassing its constituent components such as the sequencer, driver, monitor, and more.
UVM Agent

Chapter - Mar 31, 2014 by Verification Methodology Team

A UVM agent is a verification component "kit" for a given logical interface such as APB or USB.
Emulation

Chapter - Mar 31, 2014 by Verification Methodology Team

Learn all about methodology related to Veloce/TBX Emulation on UVM.
Using a Parameter Package

Chapter - Mar 31, 2014 by Verification Methodology Team

When a DUT or interface is parameterized, the parameter values are almost always used in the testbench as well.
Macro Cost-Benefit Analysis

Chapter - Mar 31, 2014 by Verification Methodology Team

Macros can be useful to reduce repetitive typing of small pattern-like code segments, to hide implementation differences or limitations among the simulators from different vendors, or to make critical code segments less error-prone for reuse.
SystemVerilog Performance Guidelines

Chapter - Mar 31, 2014 by Verification Methodology Team

These guidelines are aimed at enabling you to identify coding idioms that are likely to affect testbench performance.
UVM Sequence Items

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM stimulus generation process is based on sequences controlling the behavior of drivers by generating sequence_items and sending them to the driver via a sequencer.
Register Package

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM register model provides a way of tracking the register content of a DUT and a convenience layer for accessing register and memory locations within the DUT.
UVM Guidelines

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM library is both a collection of classes and a methodology for how to use those base classes.
Register Layer Adapter

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM register model access methods generate bus read and write cycles using generic register transactions.
UVM Performance Guidelines

Chapter - Mar 31, 2014 by Verification Methodology Team

Although the UVM improves verification productivity, there are certain aspects of the methodology that should be used with caution, or perhaps not at all, when it comes to performance and scalability considerations.
Register-Level Scoreboards

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM register model shadows the current configuration of a programmable DUT and this makes it a valuable resource for scoreboards that need to be aware of the current DUT state.
Sequence Driver Connection

Chapter - Mar 31, 2014 by Verification Methodology Team

The transfer of request and response sequence items between sequences and their target driver is facilitated by a bidirectional TLM communication mechanism implemented in the sequencer.
C Based Stimulus

Chapter - Mar 31, 2014 by Verification Methodology Team

Using c to generate stimulus via the UVM register package.
Predictors

Chapter - Mar 31, 2014 by Verification Methodology Team

A Predictor is a verification component that represents a "golden" reference model of all or part of the DUT functionality.
SystemVerilog Guidelines

Chapter - Mar 31, 2014 by Verification Methodology Team

The SystemVerilog coding guidelines and rules in this article are based on Siemens EDA's experience and are designed to steer users away from coding practices that result in SystemVerilog that is either hard to understand or debug.
Generating Stimulus with UVM Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

The uvm_sequence_base class extends the uvm_sequence_item class by adding a body task method.
Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

Sequences are used to encapsulate stimulus, Sequencer/Driver hookup, pipelined protocols, test generation, performance analysis and much more.
Unidirectional Protocols

Chapter - Mar 31, 2014 by Verification Methodology Team

For a driver, composed of a BFM-proxy pair in the dual domain testbench, the driver proxy controls the flow of sequence_items by using get_next_item() to obtain the next sequence_item to be processed, and making the item_done() call only once it has finished processing the item.
Sequence-Driver Use Models

Chapter - Mar 31, 2014 by Verification Methodology Team

Sequence-Driver Use Models can be applied to both pipelined and non-pipelined models in hardware verification.
Driver Sequence API

Chapter - Mar 31, 2014 by Verification Methodology Team

The uvm_driver is an extension of the uvm_component class that adds an uvm_seq_item_pull_port which is used to communicate with a sequence via a sequencer.
Bidirectional Protocols

Chapter - Mar 31, 2014 by Verification Methodology Team

For a driver, composed of a BFM-proxy pair in the dual domain testbench, one of the most common sequence-driver use cases is where the sequencer sends request sequence_items to the driver proxy, which then executes the request phase of the pin-level protocol through the driver BFM.

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Upcoming Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

Search Results

Filters

Advanced Search

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team