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Optimizing Emulator Utilization

Article - Jun 16, 2014 by Russell Klein

Emulators, like Siemens EDA Veloce, are able to run designs in RTL orders of magnitude faster than logic simulators. As a result, emulation is used to execute verification runs which would be otherwise impractical in logic simulation.
UVM 1.2 Class Reference

Resource (Reference Documentation) - Jun 13, 2014 by

v1.2 The UVM Class Library provides the building blocks needed to quickly develop well-constructed and reusable verification components and test environments in SystemVerilog. This UVM Class Reference provides detailed reference information for each user-visible class in the UVM library. For additional information on using UVM, see the UVM User’s Guide located in the top level directory within the UVM kit.
Stories of an AMS Verification Dude: Putting Stuff Together

Article - Jun 12, 2014 by Verification Horizons
Taming Power Aware Bugs with Questa®

Article - Jun 12, 2014 by Verification Horizons
Assertions Instead of FSMs/logic for Scoreboarding and Verification

Article - Jun 12, 2014 by Ben Cohen

Monitors, scoreboards, and verification logic are typically implemented using FSMs, logic, and tasks. With UVM, this logic is hosted in classes. This article demonstrates another option of implementing some monitors and scoreboards using SVA assertions hosted in SV interfaces.
DDR SDRAM Bus Monitoring using Mentor Verification IP

Article - Jun 12, 2014 by Verification Horizons
Simulation + Emulation = Verification Success

Article - Jun 12, 2014 by Verification Horizons
UVM 1.2 is Coming, so be Prepared

Webinar - May 15, 2014 by Tom Fitzpatrick

In this session, you will learn everything you need to know about the future of UVM including new features, performance, backward-compatibility concerns and more.
Verification Cookbook Glossary

Chapter - Mar 31, 2014 by Verification Methodology Team

This page is an index to the glossary of various terms defined and used in the Cookbook.
Sequence Library

Chapter - Mar 31, 2014 by Verification Methodology Team

Updating your VIP/testbench sequence library is one task that you may have to perform while migrating from OVM to UVM.
Convert Phase Methods

Chapter - Mar 31, 2014 by Verification Methodology Team

Part of the OVM to UVM conversion process is to change the method names for OVM phase methods (build, connect, run, etc) to the new UVM signature for phase methods.
Migrating from OVM to UVM

Chapter - Mar 31, 2014 by Verification Methodology Team

A Roadmap for upgrading to UVM - this guide covers the minimum steps to upgrade your VIP and testbench from OVM to UVM compatibility, then goes into more detail on some further steps for UVM conformance.
Questa Compiling UVM

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM class library is an open source SystemVerilog package that relies on DPI c code in order to implement some of the library features such as regular expression matching and register backdoor accesses.
Deprecated Code

Chapter - Mar 31, 2014 by Verification Methodology Team

Accellera UVM1.0 used OVM2.1.1 as it's basis, with the intention of preserving backwards compatibility where possible.
Phase Aware

Chapter - Mar 31, 2014 by Verification Methodology Team

OVM code can be ported to run on the UVM.
Arbitrating Between Sequences

Chapter - Mar 31, 2014 by Verification Methodology Team

The uvm_sequencer has a built-in mechanism to arbitrate between sequences which could be running concurrently on a sequencer.
UVM Configuration Database

Chapter - Mar 31, 2014 by Verification Methodology Team

The UVM_config_db class is the recommended way to access the resource database.
Sequence API

Chapter - Mar 31, 2014 by Verification Methodology Team

A uvm_sequence is derived from an uvm_sequence_item and it is parameterized with the type of sequence_item that it will send to a driver via a sequencer.
Reporting Verbosity

Chapter - Mar 31, 2014 by Verification Methodology Team

UVM provides a built-in mechanism to control how many messages are printed in a UVM based testbench. This mechanism is based on comparing integer values specified when creating a debug message using either the uvm_report_info() function or the `uvm_info() macro.
Built in Debug

Chapter - Mar 31, 2014 by Verification Methodology Team

Learn about various debug techniques and support for SystemVerilog and UVM with features supplied with the UVM to assist in common problem debug.
Matlab Integration

Chapter - Mar 31, 2014 by Verification Methodology Team

MATLAB is a modeling tool often used to develop functional models of complex mathematical functions which will then be translated into RTL library blocks.
UVM Phasing

Chapter - Mar 31, 2014 by Verification Methodology Team

Phasing is a stepwise construction approach of a verification environment at runtime and the execution of required stimulus and completion of the test. UVM has an API enabling components to participate in this step by step process. The construction of structured test environments with TLM connections is done in a predetermined manner to enable smart hierarchy and connectivity management. Most verification environments use the simplest possible subset of the available phases: build, connect, run.
Accessing Configuration Resources from a Sequence

Chapter - Mar 31, 2014 by Verification Methodology Team

Sequences often need access to testbench resources such as register models or configuration objects.
Testbench Configuration

Chapter - Mar 31, 2014 by Verification Methodology Team

One of the key tenets of designing reusable testbenches is to make testbenches as configurable as possible. Doing this means that the testbench and its constituent parts can easily be reused and quickly modified (i.e. reconfigured).
UVM Packages

Chapter - Mar 31, 2014 by Verification Methodology Team

A package is a SystemVerilog language construct that enables related declarations and definitions to be grouped together in a package namespace.

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

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Streamlining FPU Verification with an Alternative to C-reference Model Approaches

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Explore How to Protect Against Data Corruption with Formal Security Verification

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Article - Jun 16, 2014 by Russell Klein

Resource (Reference Documentation) - Jun 13, 2014 by

Article - Jun 12, 2014 by Verification Horizons

Article - Jun 12, 2014 by Verification Horizons

Article - Jun 12, 2014 by Ben Cohen

Article - Jun 12, 2014 by Verification Horizons

Article - Jun 12, 2014 by Verification Horizons

Webinar - May 15, 2014 by Tom Fitzpatrick

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team

Chapter - Mar 31, 2014 by Verification Methodology Team