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UVM Framework

Track - Feb 26, 2018 by Bob Oden

In this track you will learn more about UVM Framework and how it that provides a reusable UVM methodology and code generator for rapid testbench generation.
Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?

Webinar - Dec 12, 2017 by Neil Bulman

This session will describe useful debug techniques for debugging a UVM testbench with 8 to 10 agents, and many stimulus generators, checkers and exception handlers running in parallel.
How Static and Dynamic Failure Analysis Can Improve Productivity in the Assessment of Functional Safety

Article - Dec 05, 2017 by Dan Alexandrescu, Adrian Evans, Maximilien Glorieux - IROC Technologies

In this article, we present a working example, implemented using the Questa Verification Platform where a 32-bit RISC V CPU has been subjected to an extensive static and dynamic failure analysis process, as a part of a standard-mandated functional safety assessment.
Step-by-Step Tutorial for Connecting Questa VIP into the Processor Verification Flow

Article - Dec 05, 2017 by Marcela Zachariasova, Lubos Moravec - Codasip, Ltd.

This article describes verification of RISC-V processors, focusing on the combination of automatically generated UVM verification environments by QVIP Configurator and Questa® VIP (QVIP) components. The section with step-by-step instructions will demonstrate how to add QVIP components into processor verification environments.
PA GLS: The Power Aware Gate-level Simulation

Article - Dec 05, 2017 by Progyna Khondkar

In post-synthesis, gate-level netlist (GL-netlist), power aware (PA) simulation, the fundamental focus is to identify PA specific cells already present in the netlist. The associated UPF with the netlist design, determines the supply network and power connectivity to these special PA cells, and aid to keep their outputs from being corrupted. Hence, the GL-netlist-based power aware simulation (PA-SIM) input requirements are mostly the same as for RTL simulation.
Reset Verification in SoC Designs

Article - Dec 05, 2017 by Kurt Takara

Modern system-on-chip (SoC) designs contain a high level of complexity in the reset distribution and synchronization circuitry. Verifying that a design can be correctly reset under all modes of operation presents a significant challenge. In this article, we present the commonly occurring issues that are involved in reset tree verification and solutions to address them.
Debugging Inconclusive Assertions and a Case Study

Article - Dec 05, 2017 by Jin Hou

In this article, we discuss the flow to debug inconclusive assertions and use an ECC design as an example to show a decomposition technique for handling inconclusive assertions.
Separating Test Intent from Design Details with Portable Stimulus

Article - Dec 05, 2017 by Matthew Ballance

The emerging Accellera Portable Stimulus Standard (PSS) provides features that enable test writers to maintain a strong separation between test intent (the high-level rules bounding the test scenario to produce) and the design-specific tests that are run against a specific design. This article shows how Accellera PSS can be used to develop generic test intent for generating memory traffic in an SoC, and how that generic test intent is targeted to a specific design.
UVM Connect 2.3.1 Primer

Resource (Reference Documentation) - Nov 08, 2017 by John Stickley
UVM Connect 2.3.1 Primer

Resource (Reference Documentation) - Nov 08, 2017 by John Stickley
UVM Connect 2.3.1 Kit

Resource (Tarball) - Nov 07, 2017 by John Stickley
An Introduction to DO-254 and Advanced Verification

Webinar - Nov 02, 2017 by Tom Fitzpatrick

DO-254 describes the objectives of a verification process to allow the development of systems that meet your design assurance goals. This web seminar will explain the critical aspects of a DO-254-compliant process and show how many advanced verification techniques and tools may be applied to satisfy these objectives.
DO-254 for FPGAs

Resource (Slides (.PDF)) - Oct 17, 2017 by Alex Grove - Siemens EDA

The goals of verification are to show that the design does what it's supposed to do and show that the design does not do anything it's not supposed to do.
Coverage & Plan Driven Verification for FPGAs Session

Resource (Slides (.PDF)) - Oct 17, 2017 by
Regression Management and Dev Ops

Resource (Slides (.PDF)) - Oct 17, 2017 by
FPGA Verification Introduction

Resource (Slides (.PDF)) - Oct 17, 2017 by
Testbench Acceleration

Resource (Slides (.PDF)) - Oct 17, 2017 by
Advanced Verification for FPGAs

Resource (Slides (.PDF)) - Oct 17, 2017 by Brian Mathewson

Industry Trends and Challenges for FPGA Development
Accelerating Coverage Closure

Resource (Slides (.PDF)) - Oct 17, 2017 by Mark Handover

In this session, you will learn why Coverage Closure ranks at the top of FPGA verification challenges and how you can improve coverage quality.
Measuring ISO 26262 Metrics of Analog Circuitry in ICs

Resource (Paper (.PDF)) - Oct 10, 2017 by Stephen Sunter - Siemens EDA

A “safety mechanism” in ISO 26262 terminology is a technical solution that monitors, tests for, or controls faults in a safety-related function to assert or maintain a safe state.
Measuring ISO 26262 Metrics of Analog Circuitry in ICs

Paper - Oct 10, 2017 by Stephen Sunter - Siemens EDA

This paper first discusses these metrics and their relationship to each other. Then it discusses how to measure each of the metrics with Tessent DefectSim.
Handling Inconclusive Assertions in Formal Verification

Track - Oct 10, 2017 by Jin Hou

In this track, you will be introduced to techniques to help formal tools solve inconclusive assertions. You will also learn tool options to help convergence, introduce techniques for reducing assertion and design complexity.
Editor Insight

Session - Oct 10, 2017 by Harry Foster

This editor insight session provides an introduction and motivation for our new track, which is focused on handling inconclusive assertions in formal property checking.
Easy Solutions

Session - Oct 10, 2017 by Jin Hou

In this session you will be introduced to easy solutions for handling inconclusive assertions by exploring tool options, and how to know where formal is stuck at.
Assertion Complexity Reduction

Session - Oct 10, 2017 by Jin Hou

In this session you will be introduced to the techniques that reduce the complexity of assumptions and checkers for formal verification, including under-constraining, over-constraining, assertion decomposition, adding “helper” assertion, assume-guarantee, and Questa® QFL assertion libraries.