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Block level testbench
Resource (Tarball) - Apr 02, 2019 by
Example of a block level UVM testbench
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Debugging Inconclusive Assertions and a Case Study
Article - Mar 28, 2019 by Jin Hou
Formal assertion-based verification uses formal technologies to analyze if a design satisfies a given set of properties. Formal verification doesn’t need simulation testbenches and can start much earlier in the verification process. There are three possible results for an assertion after formal runs: “proven,” “fired,” and “inconclusive.”
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Five Steps to Quality CDC Verification
Paper - Mar 13, 2019 by Ping Yeung
With the number of clock domains increasing in today’s complex ASIC designs, the ability to thoroughly verify clock domain crossings (CDC) has become even more important. As in functional verification, to ensure CDC issues are thoroughly verified, a comprehensive test plan is essential. Based on our experience working with many customers, we developed a five-step planning process for CDC verification.
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Formal Apps Take the Bias Out of Functional Verification
Paper - Mar 13, 2019 by Bill Au
An increasingly popular approach has been to employ a comprehensive, constrained-random, coverage driven testbench development flow, such as the Universal Verification Methodology (UVM). Indeed, when random stimulus generation is well executed it often finds bugs “that no one thought of.” However, this method’s success is limited to smaller DUTs as it is essentially impossible to do an exhaustive analysis of large, complex DUTs within a realistic project schedule.
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Five Steps to Quality CDC Verification
Resource (Technical Paper) - Mar 13, 2019 by Ping Yeung
After having a CDC test plan, an effective CDC verification methodology should include structural, protocol, and metastability verification. This ensures that CDC signals are handled reliably at the design stage, avoiding costly respins after they are fabricated. We will outline how these are applied to block-level and top-level RTL modules.
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Formal Apps Take the Bias Out of Functional Verification
Resource (Technical Paper) - Mar 13, 2019 by Bill Au
When we spend hours, days, or even weeks putting our hearts and minds into creating something, we have a tendency to emphasize its strengths and minimize its weaknesses. This why verification engineers have a blind spot for their own verification platforms. This blindspot, or bias, often leads to overlooking those areas where bugs may lurk, only to emerge at the worst possible time when errors are most costly and take longer to fix.
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Technical Paper: UVM and C Tests - Perfect Together
Resource - Mar 03, 2019 by
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Coverage Data Exchange Is No Robbery…Or Is It?
Resource - Feb 28, 2019 by
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Effective Elements List and Transitive Natures of UPF Commands
Resource (Technical Paper) - Feb 28, 2019 by
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The Big Brain Theory: Visualizing SoC Design and Verification Data
Resource (Technical Paper) - Feb 28, 2019 by
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Using Strong Types in SystemVerilog Design and Verification Environments
Paper - Feb 28, 2019 by Dave Rich
One of the classic debates in computer science is whether a language should have a strongly-or weakly-typed data system. A strongly-typed language does not allow operations on data that are of incompatible types. Having strong types, as in VHDL, helps define intent and avoid errors, but is much more verbose.
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Efficient Modeling Styles and Methodology for Gate-Level Design Verification
Paper - Feb 28, 2019 by Rohit Jain
In this paper, we will discuss the various methodologies and flows available for gate-level timing simulations and the scenarios that each flow is suitable for. This will help designer/validation engineers understand what these flows mean and make informed decisions when setting up a gate-level validation process; such as, what different timing modes (zero delay, unit delay, negative delay, etc.) should be used under what circumstances.
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Efficient Modeling Styles and Methodology for Gate-Level Design Verification
Resource (Technical Paper) - Feb 28, 2019 by Rohit Jain
The exploding complexity of IC systems have contributed to the increase in challenges to verifying these designs. It is not uncommon to find designs that contain anywhere from a few million gates to hundreds of millions of gates, straining the limits of functional verification based on traditional simulation technologies.
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Formal Techniques for Optimizing ISO 26262 Fault Analysis
Paper - Feb 28, 2019 by Doug Smith
The automotive safety standard, ISO 26262 [1] , states that safety analyses on hardware designs should include Failure Mode and Effects Analysis (FMEA). Hardware architectural metrics are required to assess the adequacy of the safety mechanisms and their ability to prevent faults from reaching safety critical areas. A process of fault analysis that includes fault injection is crucial for measuring and verifying the assumptions of the FMEA.
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The Missing Link: The Testbench to DUT Connection
Resource (Technical Paper) - Feb 28, 2019 by Dave Rich
This paper focuses on several methodologies used in practice to connect the testbench to the DUT. The most common approach is the use of SystemVerilog’s virtual interface. This is so common that people fail to investigate other methodologies that have merit in certain situations. The abstract class methodology has been presented before, but still seems to have barriers to adoption.
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The Missing Link: The Testbench to DUT Connection
Paper - Feb 28, 2019 by Dave Rich
In recent years, there has been a lot of attention given to Object Oriented Programming, Constrained Random and Coverage Driven Verification with SystemVerilog. The various openly available verification methodologies have put a lot of effort into explaining how to use these technologies within the testbench.
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Comprehensive CDC Verification Using Advanced Hierarchical Data Models
Paper - Feb 28, 2019 by Ping Yeung
To help understand the importance and impact of the HDM-based hierarchical CDC flow, we will begin with a review of the existing hierarchical CDC verification methodologies. Then, we will present the improvements of the HDM-based hierarchical CDC flow and highlight its capability for verifying reconvergence of CDC paths on complex SoCs.
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Boosting Regression Throughput by Reusing Setup Phase Simulation
Resource (Technical Paper) - Feb 28, 2019 by Rohit Jain
This paper will discuss how to write the design so that the common initial setup phase simulation is done once and then used as a foundation to run different tests later on, including the ability to change test stimulus to simulate different test behaviors. We will also discuss what type of designs (Verilog, VHDL, SystemVerilog, UVM-based, SystemC, C/C++ models, PLI/FLI/VPI etc.) will fit in this methodology and what a designer can do to make his design fit for such methodology.
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Clock-Domain Crossing Challenges in Latch Based Designs
Resource (Technical Paper) - Feb 28, 2019 by Kurt Takara
This paper describes the challenges in CDC analysis for latch-based designs and a systematic approach to handle latches that are not enabled by clock signals. It also presents the results and insights of latch-based crossings for several industrial scale designs.
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Clock-Domain Crossing Challenges in Latch-Based Designs
Paper - Feb 28, 2019 by Kurt Takara
Clock-domain crossing (CDC) analysis for registers and memories are well understood problems [1] and there are many software tools to analyze the CDC issues associated with them. However, presence of latches in the designs can complicate CDC analysis as some of the latches may act as pass through combinatorial paths through which the input signal can continuously affect the output of the latch.
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Low Power Apps: Shaping the Future of Low Power Verification
Resource (Technical Paper) - Feb 28, 2019 by
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Comprehensive CDC Verification Using Advanced Hierarchical Data Models
Resource (Technical Paper) - Feb 28, 2019 by Ping Yeung
In this paper, we describe the hierarchical data model (HDM), which is the backbone of the Questa CDC hierarchical verification solution. The HDM is equivalent to an abstract CDC model of the IP that captures the CDC intent of the block along with its integration rules. It is a generic data model that can be seamlessly reused across releases and across designs wherever the IP is reused. It can also be an performance efficient alternative to the traditional flat CDC verification flow.
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Formal Techniques for Optimizing ISO 26262 Fault Analysis
Resource (Technical Paper) - Feb 28, 2019 by Doug Smith
The automotive safety standard, ISO 26262 [1], states that safety analyses on hardware designs should include Failure Mode and Effects Analysis (FMEA). Hardware architectural metrics are required to assess the adequacy of the safety mechanisms and their ability to prevent faults from reaching safety critical areas. A process of fault analysis that includes fault injection is crucial for measuring and verifying the assumptions of the FMEA.
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Technical Paper: Are You Smarter Than Your Testbench? With a Little Work You Can Be
Resource - Feb 28, 2019 by
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Using Strong Types in SystemVerilog Design and Verification Environments
Resource (Technical Paper) - Feb 28, 2019 by Dave Rich