The Three Witches Preventing Glitch Nightmares on CDC Paths

At the RTL, we focus on identifying the clock domains and CDC paths by recognizing the CDC structures and schemes. At the gate-level, CDC paths with multiplexer or combinational logic are often prone to glitch defects that can be introduced during the synthesis, timing, and power optimization process. If CDC verification is only done at RTL, such glitch defects can easily be missed and lead to costly post-silicon chip failure.