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A Formal-based Approach for Efficient RISC-V Processor Verification

Article - Feb 24, 2023 by Laurent Arditi, Paul Sargent, Thomas Aird, Lauranne Choquin - Codasip

The openness of RISC-V allows customizing and extending the architecture and microarchitecture of a RISC-V based core to meet specific requirements. This appetite for more design freedom is also shifting the verification responsibility to a growing community of developers. Processor verification, however, is never easy. The very novelty and flexibility of the new specification results in new functionality that inadvertently creates specification and design bugs.
Jumpstart your Formal Verification with a Little Help

Article - Feb 24, 2023 by Doug Smith

An advantage of using formal verification is how quickly a formal environment can be created with a few simple properties that immediately start finding design issues. However, not all design behaviors are easily modeled using SystemVerilog's property syntax, resulting in complex or numerous properties, or behaviors that require more than just SVA. Helper code can significantly reduce the complexity of properties as well as be used to constrain formal analysis.
Resolving Metastability Issues for Multi-clock SoC Environment for I2C

Article - Feb 24, 2023 by Priyanka Changan, Darshan Sarode, Avnita Pal, Priyanka Gharat - Silicon Interfaces

This article aims to resolve metastability issues for multi-clock designs by noting the clock domains and the synchronization required for crossing the clock domains. The example SoC has an 8-bit simple Microcontroller and a Memory Module with a clock differently aligned (multi-clock) to the I2C Master and Slave. Leading to issues regarding metastability that needed to be resolved using synchronizers – currently two flip-flops using a closed-loop solution for sending and receiving clock domains.
Big Data for Verification – Inspiration from Large Language Models

Resource (Verification Horizons Blog) - Feb 24, 2023 by Dan Yu

ChatGPT, one of the most prominent Large Language Models (LLMs), has proven it is capable of human-level knowledge by passing multiple exams with faded colors: Warton’s MBA exam with a B, the US Medical Licensing Exam at the threshold, and four law school courses at the University of Minnesota with a C+. Individually, they are definitely not the best an excellent professional can achieve, but still are a good demonstration of LLMs’ strengths of appearing universally knowledgeable.
Simulating UVMF Code on Windows

Session - Feb 20, 2023 by Graeme Jessiman

In this session, you will learn how to use the UVMF Build/Compile/Run script on Windows.
Simulating UVMF Code on Windows

Resource (Slides (.PDF)) - Feb 20, 2023 by Graeme Jessiman
Generating UVMF Code on Windows

Session - Feb 20, 2023 by Graeme Jessiman

In this session, you will learn how to use the generation scripts on Windows to produce UVMF testbench source.
Generating UVMF Code on Windows

Resource (Slides (.PDF)) - Feb 20, 2023 by Graeme Jessiman
Installing Python on Windows

Session - Feb 20, 2023 by Graeme Jessiman

In this session, you will learn how to install Python on a Windows system for use with UVMF scripts.
Installing Python on Windows

Resource (Slides (.PDF)) - Feb 20, 2023 by Graeme Jessiman
UVMF Build/Compile/Run Script Introduction

Session - Feb 20, 2023 by Jonathan Craft

In this session, you will be introduced to the capabilities and use of the UVMF Build/Compile/Run script.
UVMF Build/Compile/Run Script

Resource (Slides (.PDF)) - Feb 20, 2023 by Jonathan Craft
Register Adapters, Predictors, and Tests

Resource (Slides (.PDF)) - Feb 20, 2023 by Nick Galvan
Register Adapters, Predictors and Tests

Session - Feb 20, 2023 by Nick Galvan

In this session, you will learn how to use register model adapters, predictors, and tests in UVMF.
Register Model Generation and Replacement

Session - Feb 20, 2023 by Nick Galvan

In this session, you will learn how to produce a UVM register model, applying it to a UVMF testbench.
Register Model Generation and Replacement

Resource (Slides (.PDF)) - Feb 20, 2023 by Nick Galvan
Register Model Generation and Integration

Session - Feb 20, 2023 by Nick Galvan

In this session, you will be introduced to the generation of a register model as part of a UVMF environment.
Register Model Generation and Integration

Resource (Slides (.PDF)) - Feb 20, 2023 by Nick Galvan
UVM Framework Release 2023.1

Resource (Tarball) - Feb 20, 2023 by Bob Oden

General Updates: Added BASE_T type parameter to scoreboard classes to allow insertion of user base class. Added supper.xxx_phase calls to classes with BASE_T type parameter.
UVMF -All

Resource (Tarball) - Feb 14, 2023 by Bob Oden

UVMF v2023.4_2 Generator Updates: Replaced new with factory create for construction of broadcasted transaction from monitor.
Verification Data Analytics with Machine Learning

Paper - Jan 25, 2023 by Dan Yu

Verification is data-and computation-intensive, making it an ideal field for ML applications. Advancements in ML have offered many opportunities to accelerate verification workflow, improve verification quality, and automate verification execution. However, being a data-centric method, ML has also elevated data to become the most crucial factor of ML success.
Verification Data Analytics with Machine Learning

Resource (Paper (.PDF)) - Jan 25, 2023 by Dan Yu

This whitepaper provides an overview on the importance of data to ML, the available data for verification, and the existing applications of ML in verification. It reveals that data itself may dictate applicable ML models. Machine learning has demonstrated great potential in verification. However, attention should be paid to generalizing and scaling the models to ensure their success in a production environment.
The UVM Factory Revealed - Part 2

Resource (Verification Horizons Blog) - Jan 25, 2023 by Chris Spear

This is a follow up to last week’s high-level post on the UVM Factory . Now let’s get technical! Here are the SystemVerilog Object-Oriented Programming concepts behind the factory.
Epilogue: 2022 Study Summary and Key Findings

Resource (Verification Horizons Blog) - Jan 23, 2023 by Harry Foster

This is the last in a sequence of blogs that presents the findings from our new 2022 Wilson Research Group Functional Verification Study. I opened this blog series with a Prologue posting that provided an overview of this year’s study. I think it is only fitting that I end this series with an Epilogue posting that summarizes some of this year’s key findings.
FPGA Functional Verification Trend Report - 2022

Resource (Paper (.PDF)) - Jan 23, 2023 by Harry Foster

This report examines the trends in functional verification for the field programmable gate array (FPGA) market segments identified in the 2022 Wilson Research Group study.