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Simulating AMD’s Next-gen Versal Adaptive SoC Devices using QuestaSim
Resource (Slides (.PDF)) - Jul 24, 2024 by Fan Zhang
In this session, we aim to provide an in-depth guide on running simulation flows for a Versal Adaptive SoC. Additionally, we'll delve into QEMU, the open-source system emulator, and its co-simulation interface with Questa. Demonstrating how to conduct a system simulation of a Versal example design will be a focal point, showcasing Questa’s support for system simulation of Versal designs based on the Vitis™ hardware emulation flow.
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Questa CDC-FX: Metastability Effects Delay Modeling
Paper - Jun 28, 2024 by Kurt Takara
In this paper, we survey traditional metastability effect models and discuss the shortcomings of each of them. We then present the model used by Questa CDC-FX, from Siemens EDA, and describe why it is a more accurate and complete metastability-effects model.
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Questa CDC-FX: Metastability Effects Delay Modeling
Resource (Paper (.PDF)) - Jun 28, 2024 by Kurt Takara
This paper describes why metastability occurs in designs with asynchronous clocks and analyzes the various methods that designers use to verify that their design is resilient with respect to the effects of metastability. It discusses the efficacy of each of these methods and describes in detail the behavioral model of metastability that is used in the Siemens EDA Questa clock-domain-crossing verification solution.
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Introducing Smart Verification: Unleashing the Potential of AI within Functional Verification
Conference - Jun 24, 2024 by Tom Fitzpatrick
In this session, you will learn that leveraging the power of AI and ML, Smart Verification revolutionizes functional verification by using faster engines that complement traditional heuristics with machine learning. Allowing engineers to be more productive with advanced creation, analysis, and debugging capabilities, while reducing workloads through predictive technologies that streamline and accelerate the verification process.
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Accelerated Confidence in Interface Designs Mixing Software Layers, Hardware Protocols, Physical Connections
Conference - Jun 24, 2024 by Gordon Allan
In this session, you will learn that today high performance compute fabrics are spread over multiple die, multiple packages, multiple cards and racks in the data center. They are linked together by layers of CPU-to-CPU, cache-to-cache, and network node-to-node infrastructure. Those connections are based on standardized protocols, always evolving and improving, and increasingly having both a hardware interaction of multiple layers, plus one or more software layers.
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Portable Stimulus and Verification IP Fit Together Like a Hand in a Glove
Conference - Jun 24, 2024 by Tom Fitzpatrick
In this session, you will learn that the Portable Stimulus Standard (PSS) encourages verification engineers to focus on describing test scenarios, without worrying about the underlying target environment on which the test will ultimately be run. By describing the scenarios in terms of a randomizable schedule of actions, or behaviors that will execute, the test can easily be retargeted to different implementations for different environments.
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Challenges of Developing IPs for AI Chips
Conference - Jun 24, 2024 by Tom Fitzpatrick
Tom Fitzpatrick interviews Rambus VP of Engineering Susheel Tadikonda about the high-level D&V challenges of developing IPs for the new breed of AI accelerator chips; including the need to support a high-degree of IP configurability, 3DIC-specific protocol requirements that call for new levels of security for data in-motion and at rest.
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VA Live - Huntsville: Introduction and Welcome
Resource (Slides (.PDF)) - Jun 06, 2024 by Todd Holbrook
Welcome to Verification Academy Live.
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VA Live - San Diego: Introduction and Welcome
Resource (Slides (.PDF)) - Jun 06, 2024 by Todd Holbrook
Welcome to Verification Academy Live.
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VA Live - El Segundo: Introduction and Welcome
Resource (Slides (.PDF)) - Jun 06, 2024 by Todd Holbrook
Welcome to Verification Academy Live.
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VA Live - Westford: Introduction and Welcome
Resource (Slides (.PDF)) - Jun 06, 2024 by Todd Holbrook
Welcome to Verification Academy Live.
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Learn about the Security-critical CMA/SPDM, DOE, IDE, and TDISP elements of the PCIe protocol at the 2024 PCI SIG DevCon
Resource (Verification Horizons Blog) - Jun 04, 2024 by Joe Hupcey
The Peripheral Component Interconnect Express (PCIe®) protocol is incredibly feature rich; so much so that even experienced engineers can struggle to keep up with the latest enhancements and capabilities. Hence, the “PCI SIG” standards organization holds an annual conference for D&V engineers to learn directly from the industry’s PCIe experts via technical training sessions; sharing best practices to ultimately improve product roll-out and interoperability.
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The New Leader in Verification IP: Questa + Avery Solutions
Resource (Slides (.PDF)) - Jun 04, 2024 by Rick Schmidt - Siemens EDA
Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.
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Mark your calendar for the 2024 DAC-Chips to Systems Conference
Resource (Verification Horizons Blog) - May 28, 2024 by Harry Foster
Get ready and mark your calendars for DAC 61 – the Chips to Systems Conference you won’t want to miss! As the ultimate event for all things chips to systems, DAC offers top-notch training, education, exhibits, and unbeatable networking opportunities for designers, researchers, tool developers, and vendors alike. This year, we’re thrilled to announce that Siemens is DAC’s first-ever Diamond Sponsor, shining bright at booth #2521.
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Questa RDC Assist: Accelerate Reset Closure with AI/ML
Webinar - May 22, 2024 by Farhad Ahmed
In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.
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Questa RDC Assist – Improving Designer Productivity and Enabling Faster RDC Verification Closure with Machine Learning
Resource (Slides (.PDF)) - May 22, 2024 by Farhad Ahmed
In this session, you will learn how RDC Assist helps users expedite their RDC Analysis and will discuss use models and best practices to utilize RDC Assist, and walk through a demo showing its power.
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Improve Productivity and Deliver Hardware Assurance: Stimulus-free Verification
Resource (Slides (.PDF)) - May 21, 2024 by Chris Giles
Learn how Siemens' and OneSpin have combined to deliver a best-in-class Static & Formal solution with a focus on addressing unsolved industry challenges. These solutions enable teams to achieve peak performance and deliver absolute hardware assurance.
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Functional Monitoring: From Lab to In-Life
Resource (Slides (.PDF)) - May 21, 2024 by Fady Abushahla - Siemens EDA
In this session, you will learn how Tessent Embedded Analytics helps deal with the systemic complexity of large SoCs, providing intimate visibility of the real-world behavior of entire systems.
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Navigating Reset Domain Crossings to Safety in Complex SoCs
Resource (Verification Horizons Blog) - May 21, 2024 by Reetika - Siemens EDA
As the complexity of system-on-chip (SoC) designs escalates, driven by the demand for more integrated functionalities and higher performance, electronic components such as processors, power management blocks, and DSP cores are proliferating. This surge necessitates a shift towards intricate power and performance management strategies, often incorporating several asynchronous and soft resets.
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Beyond Speed: Unlocking Productivity in Simulation and Debug
Resource (Slides (.PDF)) - May 21, 2024 by Moses Satyasekaran
Gone are the days when functional verification tools were solely measured by their performance metrics. The spotlight has shifted towards productivity in today's fast-paced development environment. In this session we explore how Siemens EDA prioritizes productivity and performance, enabling customers to optimize their verification cycles and swiftly uncover bugs. Discover the transformative impact of this paradigm shift on accelerating design validation and achieving faster time-to-market.
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Questa Verification IQ: Boost Verification Predictability and Efficiency with Collaboration, Traceability, and AI/ML Analytics
Resource (Slides (.PDF)) - May 21, 2024 by Austin Mam
This session will cover Questa Verification IQ (VIQ), the next-generation, data-driven verification solution from Siemens EDA that transforms the verification process using collaboration, traceability, and analytics. VIQ enables greater collaboration among teams and utilizes machine learning and AI to boost verification productivity and efficiency.
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The New Leader in Verification IP: Questa + Avery Solutions
Resource (Slides (.PDF)) - May 21, 2024 by Kamlesh Mulchandani
Now that our acquisition of Avery Design Systems is complete, Siemens EDA is the new leader for Verification IP in the industry. This session will describe the protocol and memory verification solutions you need for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive, or Aerospace and Defense applications.
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From Chaos to Order: Using Continuous Integration for Hardware Functional Verification
Paper - May 13, 2024 by Dr. Abdelouahab Ayari
In recent years, continuous integration and development have become crucial in organizing software development cycles. As a result, it has also become a way to streamline hardware flow, especially with the increased complexity of chips and SoCs. This paper discusses the ability of hardware CI flow to accelerate the functional verification flow and increase productivity and quality.
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From Chaos to Order: Using Continuous Integration for Hardware Functional Verification
Resource (Paper (.PDF)) - May 13, 2024 by Dr. Abdelouahab Ayari
Continuous integration plays an important role in organizing the hardware flow and making integration seamless, easy, and trackable using the ability of running multiple jobs in parallel it is capable of accelerating the workflow. This paper discusses the ability of hardware CI flow to accelerate the functional verification flow and increase productivity and quality.
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Without Objection: Touring the uvm_objection Implementation - Uses and Improvements
Resource (Paper (.PDF)) - May 13, 2024 by Rich Edelman
This paper will explain uvm_objections implementations, share uses and provide some alternative solutions that are easier to understand, simpler to use, and work transparently.