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When Regular CDC Is Not Enough: Reset Domain Crossing Verification and Hierarchical Data Modeling (HDM)
Resource (Slides (.PDF)) - May 31, 2023 by Kevin Campbell
In this session, you will learn more about RDC and how to accelerate your CDC with hierarchical data models.
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A multi-dimensional view of formal verification coverage
Resource (Slides (.PDF)) - May 31, 2023 by Nicolae Tusinschi
In this session, you will learn more about formal coverage and verification coverage integration advantages.
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Advanced CDC flows: Dynamic Metastability Modeling, Protocol Verification, Reconvergence
Resource (Slides (.PDF)) - May 31, 2023 by Kevin Campbell
In this session, you will learn more how dynamic CDC addresses static CDC limitations, and how to benefit from CDC transfer protocols and structural reconvergence verification.
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Enhancing CDC flows with Machine Learning (ML) today, and the future roadmap of static solutions
Resource (Slides (.PDF)) - May 31, 2023 by Kevin Campbell
In this session, you will learn why Siemens EDA is investing in the power of machine learning (ML) in static & formal verification to increase efficiency and confidence.
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osmosis Aerospace and Defense 2023
Conference - May 30, 2023 by Martin Rowe
osmosis Aerospace and Defense (A&D) is about sharing the success in using formal techniques to address the demanding verification requirements and challenges of Trust and Assurance verification, Safety Critical Designs, and DO-254 compliant and other high-consequence systems.
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Bent Tools and other Horrors From the Garden and UVM Debug – or Are You Still Debugging with $display?
Resource (Verification Horizons Blog) - May 24, 2023 by Rich Edelman
I can’t take credit for the great flowers in the garden. It’s the tremendous rain we’ve had in California this year – and anyhow, my wife is the gardener in the house. But it’s my job to do some weeding. While meditative, it is disagreeable to me. But back to UVM Debug and Visualizer.
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Efficient Interconnect Formal Verification for Complex, Large-scale Designs
Webinar - May 17, 2023 by Nicolae Tusinschi
In this session we will show how to run design exploration for detailed connectivity specification, how to specify abstract specification that translates into machine readable specification.
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Efficient Interconnect Formal Verification for Complex, Large-scale Designs
Resource (Slides (.PDF)) - May 17, 2023 by Nicolae Tusinschi
In this session we will show how to run design exploration for detailed connectivity specification, how to specify abstract specification that translates into machine readable specification.
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Delivering First Silicon Success for Your Next SoC or 3DIC
Resource (Slides (.PDF)) - Apr 25, 2023 by Gordon Allan
Now that our acquisition of Avery Design Systems is complete, Siemens EDA are the new leaders in Verification IP in the industry. Our combined team of experts are ready to provide the industry with a complete protocol and memory verification portfolio, to bring independent, high-quality verification, standards-based solutions that are interoperable across all simulators, and quality which is already trusted by the most successful silicon teams across the globe.
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Delivering First Silicon Success for Your Next SoC or 3DIC
Webinar - Apr 25, 2023 by Gordon Allan
In this session, you will learn about the protocol and memory verification solutions needed for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive or Mil/Aero applications.
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Groups of Class Specializations in SystemVerilog
Resource (Verification Horizons Blog) - Apr 25, 2023 by Chris Spear
In a previous post , I said that in SystemVerilog, once you specialize a class, you can not make a group of them. Oops! Turns out that UVM does this all this time. You just need to know where to start. Just to be clear, you are making a group of handles, an array. Every object is separate, and thus cannot organized into an array.
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Questa Verification IQ: Boost Verification Predictability and Efficiency with Big Data
Webinar - Apr 11, 2023 by Darron May
In this session, you will learn how you can accelerate your coverage closure using VIQ’s unique predictive and prescriptive data analysis, maximizing your team's efficiency.
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Back to the Future with Formal Property Checking (PDF)
Resource - Apr 03, 2023 by
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The Digital Twin: An Aerospace and Defense Revolution
Session - Mar 29, 2023 by Ray Salemi
This session will provide a look into a seamless and comprehensive Digital Thread for Defense and the immense value it brings.
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Continuous Integration (CI) Driving Efficient Program Execution
Webinar - Mar 28, 2023 by Kevin Campbell
In this session, you will learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows.
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Continuous Integration (CI) driving efficient program execution
Resource (Slides (.PDF)) - Mar 28, 2023 by Kevin Campbell
In this session, you will learn the value of Continuous Integration during development and how Questa Design Solutions are ideally suited for implementation in CI flows.
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How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself
Webinar - Mar 18, 2023 by Joon Hong
In this session, we will show how to employ an automated, formal-based flow to ensure complete coverage of your registers’ state space – without having to learn formal at all. The benefits of this approach are two-fold: you can exhaustively verify the specified behaviors and the complete absence of any illegal behaviors.
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Practical Flows for Continuous Integration: Making The Most of Your EDA Tools
Webinar - Mar 16, 2023 by Neil Johnson
In this session, we’ll teach you how to use a collection of tools – both formal and simulation – as part of a comprehensive approach to verifying RTL and testbench changes before releasing them to your team.
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Introduction to SystemVerilog Assertions
Webinar - Mar 15, 2023 by Chris Crile
In this session, you will learn the benefits of using SystemVerilog assertions including; when and where to use assertions, language structure and implementation code examples.
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Rapid Testbench Development
Resource (Slides (.PDF)) - Mar 07, 2023 by Bob Oden
Slides covering the UVM Framework, system model refinement and automated testbench creation.
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Big Data Reimagines Verification Predictability and Efficiency
Article - Feb 24, 2023 by Darron May
Big data is a term that has been around for many years. The list of applications for big data is endless, but the process stays the same: capture, process, and analyze. With new, enabling verification solutions, big data technologies can improve your verification process efficiency and predict your next chip sign-off.
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Democratizing Digital-Centric Mixed-Signal Verification Methodologies
Article - Feb 24, 2023 by Sumit Vishwakarma
As the world of technology continues to evolve, the way we design and verify circuits is also evolving. The next-generation automotive, imaging, IoT, 5G, computing, and storage markets are driving the strong demand for increasing mixed-signal content in modern System-on-Chips (SoCs). Mixed-signal designs are a combination of tightly interwoven analog and digital circuitry. There are two main reasons for increased mixed-signal contents in today's SoC.
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Lane Margining at Receiver and its Application Through Pipe Message Bus
Article - Feb 24, 2023 by Sachin Mishra
PCI Express® (PCIe) announced its fourth generation (PCIe 4.0 standard) in year 2017.With PCIe Gen 3 the speed of operation was 8 GT/s (giga transfers per second) and error rate is manageable (10-12) but with doubling the frequency with each successive generations performance degradation become more pronounced due to variety of reasons like losses in the channels due to different components, reflections in the channel, jitter and cross talk between lanes in a multi-lane system.
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The RISC-V Verification Interface (RVVI) – Test Infrastructure and Methodology Guidelines
Article - Feb 24, 2023 by Aimee Sutton, Lee Moore, Kevin McDermott - Imperas Software
The open standard ISA of RISC-V is at the forefront of a new wave of design innovation. The flexibility to configure and optimize a processor for the unique target application requirements has a lot of appeal in emerging and established markets alike. RISC-V can address the full range of compute requirements such as an entry-level microcontroller, a support processor, right up to the state-of-the-art processor arrays with vector extensions for advanced AI applications and HPC.
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A Formal-based Approach for Efficient RISC-V Processor Verification
Article - Feb 24, 2023 by Laurent Arditi, Paul Sargent, Thomas Aird, Lauranne Choquin - Codasip
The openness of RISC-V allows customizing and extending the architecture and microarchitecture of a RISC-V based core to meet specific requirements. This appetite for more design freedom is also shifting the verification responsibility to a growing community of developers. Processor verification, however, is never easy. The very novelty and flexibility of the new specification results in new functionality that inadvertently creates specification and design bugs.