Topics tagged Clocking-Block

Topic	Replies	Views	Activity
Using interface in testbench and for modules connection SystemVerilog virtual-interface , interface , Clocking-Block	1	121	January 5, 2026
Clocking Block in UVM Driver UVM Clocking-Block	1	174	February 14, 2025
Two Clock in Clocking block UVM UVM , Clocking-Block	16	1480	July 10, 2024
False posedge event indication on a signal SystemVerilog Clocking-Block , systemverilog-interface	1	185	February 16, 2024
Why are clocking blocks preferred when when we want to drive and sample stimulus in a SystemVerilog testbench? SystemVerilog SystemVerilog , Clocking-Block , clocking-block-assignment , Clocking-Block-and-modports	2	749	February 18, 2023
Is it possible to sample a signal on the same edge on which it was driven in sv? SystemVerilog SystemVerilog , Clocking-Block , sampled-value	5	2190	November 9, 2022
It seems there is something wrong with'##2 rtr_io.cb.reset_n <= 1'b1' in Test Program since compiling tool sends error that 'a default clocking block must be specified to use the ##n timing statement'. Can someone help to correct the test program? Thx! SystemVerilog SystemVerilog , Clocking-Block , clocks-do-not-agree-in-cycle-delay-sequence-operator	4	940	May 13, 2022
UVM scheduling and the need for Clocking Blocks UVM UVM , Race-condition , Clocking-Block	2	2108	May 2, 2022
[SystemVerilog] Difference between `wait(cb.signal == 1'b1)` and `@(cb iff cb.signal == 1'b1)` SystemVerilog SystemVerilog , Clocking-Block , wait-statement , clock-synchronous , systemverilog-driver-monitor-virtual-interface-transaction	5	3537	October 1, 2021
Delay in signals at clocking block hierarchy w.r.t RTL hierarchy in waveform SystemVerilog SystemVerilog , UVM , Clocking-Block , clockingblock , input-output-skew	1	1174	March 28, 2021
Clocking block sensitivity list SystemVerilog SystemVerilog , Clocking-Block	1	973	October 29, 2020
Usage of two or more clock signals in a clocking Block SystemVerilog SystemVerilog , Clocking-Block , Skew	3	2499	February 24, 2020
How to use Generate loop inside Interface to create clocking block SystemVerilog SystemVerilog , interface , Clocking-Block , Assertions-using-Generate-Block	4	5883	May 29, 2019
Clocking block in UVM TB UVM UVM , Clocking-Block	2	1924	April 23, 2019
Why we need modports? SystemVerilog SystemVerilog , modport , virtual-interface , Clocking-Block , Bus-interface , actual-interface	2	1702	October 22, 2018
Assertion inside clocking block in SystemVerilog SystemVerilog SystemVerilog , system-verilog-assertion-SVA , Clocking-Block , Assertion-system-verilog	2	2001	September 17, 2018
Race condition beween testbench and DUT SystemVerilog SystemVerilog , Race-condition , system-verilog-testbench , Clocking-Block	3	9461	July 13, 2018
Clocking Block Skew @ Simulation Wave SystemVerilog SystemVerilog , UVM , interface , Clocking-Block , Skew , Delay	2	2892	July 7, 2018
Issue with clocking block SystemVerilog SystemVerilog , Clocking-Block , tasks-in-interface , Clocking-block-output-is-not-legal	2	2520	June 1, 2017
Clocking block doesn't update the value of the bus SystemVerilog SystemVerilog , Clocking-Block	0	1353	December 8, 2016
To understand the fundaments os SV SystemVerilog SystemVerilog , System-Verilog , program-block , Clocking-Block	4	2043	April 4, 2015