To understand the fundaments os SV

SystemVerilog
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1

What is the basic difference between Program block and Clocking block. If possible then give example.

2

First of all, you can forget about program blocks. They are an unnecessary feature of the language and I wish they could just be removed to make it simpler to learn SystemVerilog.

See Are Program Blocks Necessary?

An example of using clocking blocks can be found in my DVCon paper: The Missing Link: The Testbench to DUT Connection.

3

In reply to dave_59:

Thanks a lot.

4

In reply to Shalin Mandiwala:

One little question. What if i use program block and clocking block both like my testbench in program block and clocking block in interface file. Does it make sense?

5

In reply to Shalin Mandiwala:

You can do that as long as you understand that:

  • Using a program block in your testbench does not prevent races within your testbench
  • Do not generate any clocks within your program block
  • any tasks or functions defined in your interface that you call from your program block will execute in the reactive region
  • By using a clocking block for all communication with your dut, using a program block provides no extra features other than your simulation will exit when the program’s initial block reaches its end.