Usage of two or more clock signals in a clocking Block

SystemVerilog
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1

I recently used two clocks in a clocking block for direction and sensitivity of the multiple signals in it. This was allowed in SV as no error came. Now I want to know if there are multiple clocks entered, the skew taken for signals would be with respect to either of the clocks or both of them. Is it possible to set skew differently in such a scenario.

2

In reply to amrit_verif_singh:

From Section 14.3 of the LRM:

The clocking_event designates a particular event to act as the clock for the clocking block. The timing used to drive and sample all other signals specified in a given clocking block is governed by its clocking event.

So if your clocking_event is a combination of two clocks, then the timing is based off of what triggered the event.

3

In reply to cgales:

Thanks for your reply, but I’m still a little confused. This is a sample/example code for my query.

interface fifo_if (input bit clk_read, input bit clk_write);
  
  //SIGNALS DECLARATION
  logic [7:0] data_write, data_read;
  logic write, read, full, Empty, almost_full, almost_empty;
  logic reset_read, reset_write;
  
  //CLOCKING BLOCKS FOR DRIVER 
  clocking driver_cb @(posedge clk_read or posedge clk_write);
    default input #2ns output #2ns;
    output data_write, write, read;
    input data_read, full, Empty, almost_full, almost_empty;
  endclocking
  //MODPORTS FOR DRIVER 
  modport DRIVER (output reset_read, reset_write, clocking driver_cb);
endinterface

In this code, if ‘clk_write = 10ns’ and ‘clk_read = 5ns’, when ‘write’ is getting triggered will it’s skew will get decided according to ‘clk_write’ or ‘clk_read’ clock?

4

In reply to amrit_verif_singh:

What do you mean by “write” getting triggered? Your clocking_event is ‘posedge clk_read or posedge clk_write’. The skew is based off of the posedge of either clk_read or clk_write, whichever clock triggered.