Usage of two or more clock signals in a clocking Block

[amrit_verif_singh]

In reply to cgales:

Thanks for your reply, but I’m still a little confused. This is a sample/example code for my query.

interface fifo_if (input bit clk_read, input bit clk_write);
  
  //SIGNALS DECLARATION
  logic [7:0] data_write, data_read;
  logic write, read, full, Empty, almost_full, almost_empty;
  logic reset_read, reset_write;
  
  //CLOCKING BLOCKS FOR DRIVER 
  clocking driver_cb @(posedge clk_read or posedge clk_write);
    default input #2ns output #2ns;
    output data_write, write, read;
    input data_read, full, Empty, almost_full, almost_empty;
  endclocking
  //MODPORTS FOR DRIVER 
  modport DRIVER (output reset_read, reset_write, clocking driver_cb);
endinterface

In this code, if ‘clk_write = 10ns’ and ‘clk_read = 5ns’, when ‘write’ is getting triggered will it’s skew will get decided according to ‘clk_write’ or ‘clk_read’ clock?