Clocking block sensitivity list

SystemVerilog
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1

Hi,
I’m looking to include a signal in the sensitivity list of a clocking block (ie, in the event_or_identifier part of the clocking block) which is level sensitive .
ie,something like:
clocking driving_cb @(posedge clk or negedge reset_n or halt);

what I’m looking to achieve is when clk is gated and when reset is high but halt is true, the logic that is waiting for an event should still be triggered (@(vif.driving_cb))

I tried this but doesnt work. Is there something I’m missing here. Could someone throw some light.

Thanks

2

In reply to Ramyas:

Clocking blocks only deal with synchronous clock events. You would write this as

clocking driving_cb @(posedge clk iff (reset_n && hal)t);