False posedge event indication on a signal

[Vlad]

Hi ,
I have a signal which is part of clocking block , defined as follows :

interface my_if (input sample_clk) ;
clocking cb_clk @(posedge sample_clk);
           input sig1;
 endclocking : cb_clk 
endinterface 

I see the odd behaviour when @(posedge my_if_inst.cb_clk.sig1) is fired once clock start ticking and sig1 is high constant .
This is false indication as in my case I want to catch the rising edge of the signal .
Any ideas for this behaviour and how to avoid this .
Attaching the image when in red circle the sig1 is raised and in blue circle when clk is fired and where the @posedge is indicated

[dave_59]

It seems like you have a conflicting set of requirements. Clocking block inputs sample on your sample_clk and that synchronizes any change on cb_clk.sig1 with that clock. If you are looking for changes, asynchronous to that clock, then you don’t use a clocking block.