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Multiple dist constraints
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0
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2
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April 7, 2026
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Associative array of event
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3
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14
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April 7, 2026
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Asynchronous_FIFO Design
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1
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34
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April 2, 2026
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sv and uvm virtual interface
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1
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25
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March 31, 2026
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Question regarding the generate block
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8
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36
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March 31, 2026
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TIC TAC TOE Snapshot generation using SystemVerilog constraints
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9
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5468
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March 30, 2026
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Question regarding the scheduling order after an event is triggered
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2
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31
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March 27, 2026
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ref argument default value
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1
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31
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March 19, 2026
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Constraint for a prime number
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3
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1297
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March 16, 2026
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Bug (?) in uvm_pool
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0
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40
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March 13, 2026
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SV Assertions using $past()
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2
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84
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February 18, 2026
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How to create a SystemVerilog testbench for my ALU's parent circuit?
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2
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53
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February 18, 2026
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Formal arguments to properties / sequences
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1
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37
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February 13, 2026
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A query about push_back and pop_front
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10
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3986
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February 12, 2026
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SVA sampling of always( a ##1 b[->1] )
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6
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63
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February 8, 2026
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Vending Machine in System Verilog
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2
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222
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February 2, 2026
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Constraint Randomization Interview Question
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22
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5651
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January 25, 2026
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Interview question on constraint
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24
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12164
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January 20, 2026
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Assertion question :-
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9
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565
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January 18, 2026
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SystemVerilog constraint: unique addr across array of structs without auxiliary array
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3
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115
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January 9, 2026
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AHB Lite protocol Verification
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2
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682
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January 7, 2026
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Assertion error
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3
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72
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January 5, 2026
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Sequence which admits : No match v/s Hard Zero
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8
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430
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December 27, 2023
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Semaphore put method question
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5
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446
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December 28, 2025
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SVA to check a N-stage synchronizer output
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9
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107
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December 18, 2025
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Connection using modports with different signals
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6
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71
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December 12, 2025
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Deep copy using shallow copy
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1
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82
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December 6, 2025
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Once a certain sequence occurs that another seq shouldn't occur till simulation ends
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8
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680
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December 4, 2025
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Adding and deleting elements of dynamic type at same time
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2
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89
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November 29, 2025
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What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules?
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0
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106
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November 17, 2025
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