Type v/s Size cast within with clause of sum()

SystemVerilog
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1

Hi Dave,

(1) To constraint sum() of a random unpacked array to 32-bit value, user has an option to use either type cast ( int’ ) or size cast ( 32’ ).

rand bit [30:0] a[2];        // Could be dynamic array / Queue

rand bit signed [30:0] b[2]; // Could be dynamic array / Queue

constraint a_sum { a.sum() with (int'(item)) == 32'h... ; } // Some 32-bit value

constraint b_sum { b.sum() with (32'(item)) == 32'h... ; } // Some 32-bit value

(Q1) Is there any scenario ( size could be greater than 2 ) where type cast would be preferred over size cast or vice-versa ? By preferred I mean to say that constraint is unsatisfiable using one cast and solvable using the other cast

(2) For b_sum the resultant sum in LHS would be 32-bit signed value whereas the RHS is unsigned value due to sized literal.

constraint b_sum { 32'(signed'(final_sum)) == 32'h... ; } // Some 32-bit RHS value

(Q2) Due to presence of unsigned value in RHS, can we say that the resultant constraint expression is unsigned ?

Thanks in Advance

2

It matters whether you need to represent a number greater than 2,147,483,647. In most cases, it’s best to keep all values unsigned, so 32’() should be preferred over int’(). However, in most situations, it doesn’t matter, and int’() is more descriptive.