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P_sequencer and m_sequencer
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13
|
56123
|
April 28, 2026
|
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Difference of reset/configure/main/shutdown phases and run phase
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5
|
101
|
April 20, 2026
|
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I need to know how many UVM active/Passive agents are required
|
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4
|
80
|
April 4, 2026
|
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sv and uvm virtual interface
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1
|
48
|
March 31, 2026
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Bug (?) in uvm_pool
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0
|
56
|
March 13, 2026
|
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Back door access for uvm_mem
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3
|
1478
|
March 13, 2026
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UVM Verification of I2C Slave IP with APB Registers
|
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2
|
98
|
March 10, 2026
|
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Ensuring specific uvm_config_db::set always wins
|
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0
|
83
|
February 24, 2026
|
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Bind interface for internal DUT forcing
|
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20
|
5560
|
February 21, 2026
|
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How to create a SystemVerilog testbench for my ALU's parent circuit?
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2
|
76
|
February 18, 2026
|
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P_sequencer / m_sequencer
|
|
11
|
37039
|
February 13, 2026
|
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A query about push_back and pop_front
|
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10
|
4004
|
February 12, 2026
|
|
UVM scoreboard interview question
|
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4
|
652
|
February 12, 2026
|
|
Calling a Task at the end of run_phase
|
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3
|
114
|
January 17, 2026
|
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AHB Lite protocol Verification
|
|
2
|
707
|
January 7, 2026
|
|
Working of uvm_cmdline_processor::get_arg_matches
|
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3
|
82
|
January 6, 2026
|
|
Assertion error
|
|
3
|
80
|
January 5, 2026
|
|
Confusion with the master monitor and slave monitor functionality
|
|
3
|
110
|
December 22, 2025
|
|
UVM 1.2 new warning - a resource with meta characters in the field name has been created
|
|
12
|
7378
|
December 18, 2025
|
|
Significance of 'contxt' Argument for create() functions of uvm_component_registry N uvm_object_registry
|
|
2
|
1176
|
December 6, 2025
|
|
What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules?
|
|
0
|
128
|
November 17, 2025
|
|
UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses
|
|
2
|
93
|
November 13, 2025
|
|
Individual field access causes extra reads/writes?
|
|
5
|
57
|
November 12, 2025
|
|
Vertical re-use (from block to sub-system/chip level)
|
|
5
|
3400
|
November 2, 2025
|
|
Why uvm_object_registry is called as lightweight proxy?
|
|
1
|
82
|
October 28, 2025
|
|
UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure
|
|
5
|
159
|
October 27, 2025
|
|
Multiple analysis ports to single implementation
|
|
8
|
287
|
October 23, 2025
|
|
How to properly extend a test case from different parents
|
|
2
|
175
|
October 21, 2025
|
|
How to deep copy UVM transaction containing queue of objects?
|
|
3
|
122
|
October 21, 2025
|
|
Config db fatal isssue
|
|
1
|
113
|
October 16, 2025
|