Topics tagged UVM

Topic	Replies	Views	Activity
Using uvm_config_db::get(null, ...) Inside a UVM Sequence (uvm_object) UVM UVM	1	7	June 15, 2026
UVM Driver Communication: get_next_item()/item_done() vs get()/put() — Which is Preferred in Industry? UVM UVM	5	44	June 14, 2026
Using uvm field automation macros in uvm_object extended types UVM UVM , uvm_config_db , field-macros	1	11	June 12, 2026
Why Use convert2string() in UVM When We Can Simply Use display()? UVM UVM	1	17	June 10, 2026
UVM_SEQ_ARB_WEIGHTED Arbitration: How Does It Work and When Should It Be Used? UVM UVM	1	27	June 8, 2026
Why does UVM need both wait_for_grant() and wait_for_item_done()? UVM UVM	3	44	June 8, 2026
UVM Sequencer Arbitration: Is Sequence Priority Used During Queue Insertion or During Grant Selection? UVM UVM	3	27	June 8, 2026
For understanding factory usage UVM UVM , set_type_override , factory , Polymorhphism	6	1615	June 3, 2026
Why Is Scoreboard Kept Separate from Agent in UVM? UVM UVM	2	60	June 3, 2026
Understanding the Real Difference Between uvm_resource_db and uvm_config_db UVM UVM	2	38	June 2, 2026
Router scoreboard implementation SystemVerilog UVM , scoreboard	0	39	May 29, 2026
Why Did UVM Creators Make Separate Classes for uvm_transaction and uvm_sequence_item? UVM UVM	1	44	May 26, 2026
Confusion About uvm_void in UVM Hierarchy UVM UVM	3	50	May 26, 2026
P_sequencer and m_sequencer UVM UVM	13	56203	April 28, 2026
Difference of reset/configure/main/shutdown phases and run phase UVM UVM , UVM_PHASE , phase , UVM-phases , run_phase , uvm-run_phase , main_phase , run_phase-main_phase	5	127	April 20, 2026
I need to know how many UVM active/Passive agents are required UVM UVM	4	102	April 4, 2026
sv and uvm virtual interface SystemVerilog SystemVerilog , UVM , virtual-interface	1	61	March 31, 2026
Bug (?) in uvm_pool UVM SystemVerilog , UVM , uvm_event_pool	0	60	March 13, 2026
Back door access for uvm_mem UVM UVM	3	1503	March 13, 2026
UVM Verification of I2C Slave IP with APB Registers UVM UVM , Coverage , System-Verilog , SVA	2	113	March 10, 2026
Ensuring specific uvm_config_db::set always wins UVM UVM , uvm_config_db	0	88	February 24, 2026
Bind interface for internal DUT forcing UVM UVM	20	5595	February 21, 2026
How to create a SystemVerilog testbench for my ALU's parent circuit? UVM SystemVerilog , UVM	2	98	February 18, 2026
P_sequencer / m_sequencer UVM UVM	11	37068	February 13, 2026
A query about push_back and pop_front SystemVerilog SystemVerilog , UVM	10	4024	February 12, 2026
UVM scoreboard interview question UVM UVM , UVM-scoreboard	4	681	February 12, 2026
Calling a Task at the end of run_phase UVM UVM , UVM-phases	3	128	January 17, 2026
AHB Lite protocol Verification UVM SystemVerilog , UVM , Coverage , assertion	2	731	January 7, 2026
Working of uvm_cmdline_processor::get_arg_matches UVM UVM , uvm_cmdline_processor , get_arg_matches	3	94	January 6, 2026
Assertion error SystemVerilog SystemVerilog , UVM , assertion , SVA	3	88	January 5, 2026