Topics tagged UVM

Topic	Replies	Views	Activity
Detection of Interrupt in Monitor UVM UVM , virtual-interface , rose	0	8	July 29, 2026
Question on UVM Phases UVM UVM , UVM-phases , uvm_phases	1	32	July 24, 2026
What is the difference between uvm_config_db and uvm_resource_db? UVM UVM , uvm_config	22	43680	July 21, 2026
How do we integrate the toolchain with uvm? UVM SystemVerilog , UVM	1	61	July 2, 2026
Monitor-to-Scoreboard Connection UVM UVM	3	107	July 1, 2026
Difference between put_port and get_port? UVM UVM , put_port	8	2496	June 30, 2026
Why are UVM User-Defined Phase Classes Implemented as Singletons? UVM UVM	1	57	June 29, 2026
implement a reference counter UVM UVM	3	63	June 25, 2026
Where to implement memory read/write operations in UVM agent when observing packet transactions in monitor? UVM UVM	3	79	June 23, 2026
Using uvm field automation macros in uvm_object extended types UVM UVM , uvm_config_db , field-macros	3	38	June 23, 2026
QCX not activating with optimized UVM testbench (qsim only, no qopt -qcx license) Coverage UVM , Coverage	1	27	June 17, 2026
Using uvm_config_db::get(null, ...) Inside a UVM Sequence (uvm_object) UVM UVM	2	67	June 15, 2026
UVM Driver Communication: get_next_item()/item_done() vs get()/put() — Which is Preferred in Industry? UVM UVM	5	83	June 14, 2026
Why Use convert2string() in UVM When We Can Simply Use display()? UVM UVM	1	42	June 10, 2026
UVM_SEQ_ARB_WEIGHTED Arbitration: How Does It Work and When Should It Be Used? UVM UVM	1	59	June 8, 2026
Why does UVM need both wait_for_grant() and wait_for_item_done()? UVM UVM	3	73	June 8, 2026
UVM Sequencer Arbitration: Is Sequence Priority Used During Queue Insertion or During Grant Selection? UVM UVM	3	44	June 8, 2026
For understanding factory usage UVM UVM , set_type_override , factory , Polymorhphism	6	1634	June 3, 2026
Why Is Scoreboard Kept Separate from Agent in UVM? UVM UVM	2	85	June 3, 2026
Understanding the Real Difference Between uvm_resource_db and uvm_config_db UVM UVM	2	62	June 2, 2026
Router scoreboard implementation SystemVerilog UVM , scoreboard	0	59	May 29, 2026
Why Did UVM Creators Make Separate Classes for uvm_transaction and uvm_sequence_item? UVM UVM	1	60	May 26, 2026
Confusion About uvm_void in UVM Hierarchy UVM UVM	3	63	May 26, 2026
P_sequencer and m_sequencer UVM UVM	13	56347	April 28, 2026
Difference of reset/configure/main/shutdown phases and run phase UVM UVM , UVM_PHASE , phase , UVM-phases , run_phase , uvm-run_phase , main_phase , run_phase-main_phase	5	168	April 20, 2026
I need to know how many UVM active/Passive agents are required UVM UVM	4	110	April 4, 2026
sv and uvm virtual interface SystemVerilog SystemVerilog , UVM , virtual-interface	1	76	March 31, 2026
Bug (?) in uvm_pool UVM SystemVerilog , UVM , uvm_event_pool	0	68	March 13, 2026
Back door access for uvm_mem UVM UVM	3	1526	March 13, 2026
UVM Verification of I2C Slave IP with APB Registers UVM UVM , Coverage , System-Verilog , SVA	2	131	March 10, 2026