Topics tagged UVM

Topic	Replies	Views	Activity
Bug (?) in uvm_pool UVM SystemVerilog , UVM , uvm_event_pool	0	33	March 13, 2026
Back door access for uvm_mem UVM UVM	3	1442	March 13, 2026
UVM Verification of I2C Slave IP with APB Registers UVM UVM , Coverage , System-Verilog , SVA	2	54	March 10, 2026
Ensuring specific uvm_config_db::set always wins UVM UVM , uvm_config_db	0	67	February 24, 2026
Bind interface for internal DUT forcing UVM UVM	20	5518	February 21, 2026
How to create a SystemVerilog testbench for my ALU's parent circuit? UVM SystemVerilog , UVM	2	52	February 18, 2026
P_sequencer / m_sequencer UVM UVM	11	36997	February 13, 2026
A query about push_back and pop_front SystemVerilog SystemVerilog , UVM	10	3984	February 12, 2026
UVM scoreboard interview question UVM UVM , UVM-scoreboard	4	605	February 12, 2026
Calling a Task at the end of run_phase UVM UVM , UVM-phases	3	100	January 17, 2026
AHB Lite protocol Verification UVM SystemVerilog , UVM , Coverage , assertion	2	674	January 7, 2026
Working of uvm_cmdline_processor::get_arg_matches UVM UVM , uvm_cmdline_processor , get_arg_matches	3	73	January 6, 2026
Assertion error SystemVerilog SystemVerilog , UVM , assertion , SVA	3	69	January 5, 2026
Confusion with the master monitor and slave monitor functionality UVM UVM , SPI-Test-Plan	3	105	December 22, 2025
UVM 1.2 new warning - a resource with meta characters in the field name has been created UVM UVM , uvm_reg_block , Resource_db , UVMRSRCNOREGEX , UVM-12 , uvm-warning	12	7344	December 18, 2025
Significance of 'contxt' Argument for create() functions of uvm_component_registry N uvm_object_registry UVM UVM , Significance-of-contxt-Argument-for-create-functions-of-uvm_component_registry-N-uvm_object_registry	2	1170	December 6, 2025
What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules? UVM OVM , SystemVerilog , UVM , Coverage	0	105	November 17, 2025
UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses UVM SystemVerilog , UVM , uvm-register-model	2	91	November 13, 2025
Individual field access causes extra reads/writes? UVM SystemVerilog , UVM , uvm-register-model	5	52	November 12, 2025
Vertical re-use (from block to sub-system/chip level) UVM UVM , reuse	5	3390	November 2, 2025
Why uvm_object_registry is called as lightweight proxy? UVM UVM	1	78	October 28, 2025
UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure UVM UVM	5	134	October 27, 2025
Multiple analysis ports to single implementation UVM SystemVerilog , UVM , analysis-port	8	253	October 23, 2025
How to properly extend a test case from different parents UVM SystemVerilog , UVM	2	163	October 21, 2025
How to deep copy UVM transaction containing queue of objects? UVM SystemVerilog , UVM	3	116	October 21, 2025
Config db fatal isssue UVM OVM , SystemVerilog , UVM	1	107	October 16, 2025
Getting last transaction in consumer repetitively even though producer is sending all transaction UVM SystemVerilog , UVM	3	97	October 15, 2025
Protected registers behavior implementation with RAL UVM UVM	1	78	October 8, 2025
Loop to randomize RAL fields across multiple registers SystemVerilog UVM	0	48	October 8, 2025
How to find the functional coverage of a signal which is declared in a module. This module is instantiated 256 times UVM UVM	6	86	October 2, 2025