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Difference of reset/configure/main/shutdown phases and run phase
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2
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17
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April 12, 2026
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Wait_for_state() in a static module doesn't work as expected
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10
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173
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November 16, 2025
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Why final phase have top - down execution flow why not bottom-up?
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1
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122
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June 13, 2025
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Calling of build phase?
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26
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20948
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November 14, 2024
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Suggestions for uvm_phase API
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1
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116
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July 25, 2024
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Why pre_shutdown phase occurs at 0ns?
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1
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733
|
July 6, 2022
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How uvm phasing mechanism (behind the curtain) work ? can it be achived by systemverilog features?
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1
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598
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February 5, 2022
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Scheduling in build_phase()
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1
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700
|
September 7, 2021
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Handle as null
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4
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2487
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March 28, 2020
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What happens in the build phase?
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3
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2013
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November 2, 2016
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UVM_Phasing Clarification needed
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2
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1666
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November 13, 2015
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UVM testcase stops at the extract phase and doesnt exit simulation
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2
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2929
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December 24, 2014
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UVM phase
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3
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2029
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September 19, 2014
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Phase Doubt: build, connect, start (pre-start, start, post-start), run(......),
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2
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1938
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June 4, 2014
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UVM Phases handling question
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1
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1710
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March 31, 2014
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