Topics tagged Coverage

Topic	Replies	Views	Activity
Excluding the already defined bins Coverage SystemVerilog , Coverage , Dave-Rich	6	243	September 29, 2026
QCX not activating with optimized UVM testbench (qsim only, no qopt -qcx license) Coverage UVM , Coverage	1	83	June 17, 2026
Advantage of $future_gclk over $past in FV SystemVerilog Coverage , assertion , System-Verilog , SVA , Formal-Verification , FV	0	69	May 25, 2026
How to define coverpoint bins which are mutually exclusive each other Coverage Coverage , coverpoint , covergroup	5	1880	April 20, 2026
UVM Verification of I2C Slave IP with APB Registers UVM UVM , Coverage , System-Verilog , SVA	2	188	March 10, 2026
AHB Lite protocol Verification UVM SystemVerilog , UVM , Coverage , assertion	2	862	January 7, 2026
Code coverage : Block Coverage Coverage	0	188	November 25, 2025
Is there any way to merge two types of code coverage and show the total between them Coverage Coverage	1	218	November 21, 2025
What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules? UVM OVM , SystemVerilog , UVM , Coverage	0	213	November 17, 2025
VHDL Code Coverage - Generate Statements Coverage Coverage	1	121	November 6, 2025
Chained Implications in SVA SystemVerilog SystemVerilog , Coverage , assertion , SVA , axi , AHB	0	121	November 3, 2025
In my design, I have an assign statement like assign var = (a == b) ? 1 : 0;. During simulation, var takes both values 1 and 0 as expected, but in Questa code coverage, this statement is still shown as not covered. Why is this happening? Coverage Coverage , questasim	1	101	October 29, 2025
Coverpoint for groups of address SystemVerilog Coverage	1	123	October 10, 2025
Trying to cover the following Transition coverage SystemVerilog Coverage , Transition-Coverage	0	104	October 6, 2025
Multiple Instances of a Covergroup Coverage Coverage	5	5221	September 11, 2025
HDLBits like website to practice SystemVerilog (assertions/constraints/ some riddles)? SystemVerilog Coverage , assertion , constraint-randomization	2	676	September 2, 2025
How the sample function for collecting coverage is implemented Coverage SystemVerilog , Coverage	3	211	August 25, 2025
Does cross coverage create auto bins even if i declare few user defined bins? Coverage Coverage	2	1768	August 19, 2025
Trasition between signals Coverage Coverage	2	1194	August 19, 2025
Coverage bins sampling an uninitialized virtual interface object SystemVerilog UVM , Coverage	7	184	July 15, 2025
SV cross coverage with 'intersect' keyword SystemVerilog Coverage , cross-coverage-bins	6	255	June 26, 2025
Sample level triggered signal Coverage Coverage	6	209	June 25, 2025
Write coverage (Add ignore bin) for a 64 bit vector where the only legal values are when all the 1's are continuous. It is allowed to have 0's at either end of the vector, but there cannot be any 0's between 1's in the vector Coverage Coverage , System-Verilog , Coverage-bins , coverage-bins-uvm-array	2	1013	May 17, 2025
Functional Coverage for larger bit size SystemVerilog UVM , Coverage	1	173	May 17, 2025
Combining illegal_bins with default SystemVerilog Coverage , illegal-bins , Default-bin	1	203	May 12, 2025
How to specify coverbin for all negative integers Coverage Coverage	1	231	May 10, 2025
Create a coverpoint with its bit width varies SystemVerilog Coverage , coverpoint , covergroup	2	188	April 11, 2025
What is False Coverage and hole in coverage ? How to solve them? Coverage SystemVerilog , Coverage	1	304	April 2, 2025
Create a coverpoint to sample non default value SystemVerilog Coverage , coverpoint	2	129	April 2, 2025
Cross coverage of coverpoints sampling on different addresses SystemVerilog SystemVerilog , Coverage , cross-coverage	2	226	March 26, 2025