I am trying to create a bin & exclude the same bin value when specific variable is not set .
I’ve tried below 3 options but none of them making coverage score to 100%.
bit x, decider; // If decider is 1, then only X can be covered
Approach 1 :
--------------------
x_cp : coverpoint x iff (decider == 1) {
bins HIT = {1};
}
Approach 2 :
--------------------
x_cp : coverpoint x {
bins HIT = {1} iff (decider == 1);
}
Approach 1 :
--------------------
x_cp : coverpoint x {
bins HIT = {1};
ignore_bins IGNORE_HIT = {1} iff (decider == 0);
}
The iff
construct of a cover group, point, or bin only blocks sampling, not construction of the bins. You can achieve 100% coverage by either adding a decider to the coverpoint expression or setting its weight to zero.
cg_inst.x_cp.option.weight = 0;
or
x_cp : coverpoint x || (decider == 0) {
bins HIT = {1};
}
Thanks @dave_59 . Can weight be dynamically set to 0 ?
I tried doing it in EDA Playground, but it’s not working .
Please explain what “not working” means. Show us your example.
Sure . Below is my example
covergroup cg_y @(posedge clk);
a_y : coverpoint y {
option.weight = 0;
bins HIT = {1};
}
endgroup
initial begin
cg_y cg_inst_y = new();
decider = 0;y = 0;
for (int i = 0; i < 14; i++) begin
#10;
end
$display (“Coverage_Y = %0.2f %%”, cg_inst_y.get_coverage());
$finish();
end
In the above, coverage score is still 0%.
Can you please check ?
To use a weight=0
, you must have at least one other coverpoint or covergroup with 100% coverage. If not, you’ll need to use my second approach. Regardless of the approach, you’ll need to sample your covergroup.
Here is an example of a complete ready to run example
module top;
logic y, decider;
covergroup cg_y;
a_y : coverpoint y {
bins HIT = {1};
}
b_y: coverpoint y {
bins HIT = {0};
}
endgroup
cg_y cg_inst_y = new();
initial begin
decider = 0;y = 0;
cg_inst_y.sample();
$display ("Coverage_Y = %5.2f %%", cg_inst_y.get_coverage());
if (decider == 0)
cg_inst_y.a_y.option.weight = 0;
$display ("Coverage_Y = %5.2f %%", cg_inst_y.get_coverage());
end
endmodule