UVM Verification of I2C Slave IP with APB Registers

Hello everyone,

I am currently working on a verification project of an I2C Slave IP using UVM. The IP has an APB interface for registers access, and I am building the testbench from scratch to understand the full UVM flow.

I want to ask for advice on how to structure a testplan and testbench architecture for this project.

The Verification Academy provides a lot of information to help you get started. Have you gone through all of the training and examples?

No, there is an example with internal registers ?