Hi, I am a beginner with decent hold of basics of SV and UVM but I need more hands on practice on constraints and SVA . I’m looking for online resources (sites/repos) that provide exercise-style problems for SystemVerilog verification specifically for learning/practicing SVA, constraints, similar to how LeetCode provides problems for algorithms. HDLBits is great but its mainly for RTL Design
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Hello @dave_59 thanks you, apart from EDA Playground, are there any sites that provide guided exercises or challenges to practice SystemVerilog assertions and constraints?