Verification Academy

coverage-bins-uvm-array

Topic		Replies	Views	Activity
Write coverage (Add ignore bin) for a 64 bit vector where the only legal values are when all the 1's are continuous. It is allowed to have 0's at either end of the vector, but there cannot be any 0's between 1's in the vector Coverage Coverage , System-Verilog , Coverage-bins , coverage-bins-uvm-array		2	1011	May 17, 2025
I have small doubt in dist constraint (:/) SystemVerilog SystemVerilog , systemverilog-distribution-constraints , coverage-bins-uvm-array		1	445	September 29, 2023
How to create the cover group's bins that based on array's values Coverage Coverage , coverage-bins-uvm-array		6	1129	June 28, 2023