Why Is Scoreboard Kept Separate from Agent in UVM?

UVM
1

Why Is Scoreboard Kept Separate from Agent in UVM?

In traditional SystemVerilog testbenches, generator, driver, monitor, and scoreboard are usually placed directly inside the environment.

In UVM:

  • sequencer, driver, and monitor are grouped into an agent

  • scoreboard is kept separate inside the environment

I understand why protocol-related components are grouped into an agent, but I am confused specifically about the scoreboard.

Because scoreboards are also often protocol/DUT-specific, for example:

  • FIFO scoreboard

  • RAM scoreboard

  • AES scoreboard

  • HMAC scoreboard

  • AXI scoreboard

  • APB scoreboard

So my question is:

Why did UVM inventors keep the scoreboard separate from the agent instead of placing it inside the agent too?

What exact architectural or reusability problem does this separation solve?

2

This might just be a difference in terminology.

Scoreboards are typically connected to multiple agents to ensure the end-to-end correctness of the system. These agents analyze the flow of data through transactions.

Protocol checkers can be embedded within agents or integrated into the SystemVerilog interfaces they connect to. These checks can be implemented using assertions.

3

can you please, elaborate how i can integrate scoreboard and system verilog interface for multiple protocols ?