Question on UVM Phases

UVM
, ,
1

Hi Moderators,

I have my USB UVC Agent declared as

class usb_agent #(int XCVR_SELECT_WIDTH) extends vc_agent;
   ........
// Inherits 'm_sequencer' which is of Type Parameter of parent class of vc_agent
   virtual task run_phase(uvm_phase phase);
     super.run_phase(phase);
     if( cfg.agent_cfg.is_active && cfg.agent_cfg.start_default_seq) begin
       fork
         if( cfg.agent_cfg.agent_type inside { DEV,OTG_A_DEV,OTG_B_DEV } begin
            dev_seq dev_seq_h = dev_seq::type_id::create("dev_seq");
            dev_seq.start(m_sequencer);
         end
       join
     end
   endtask
endclass

I noticed that there is no objection raised within run_phase

Within class vc_agent and it’s super classes ( which is extended uvm_component ) I observe that there is no definition of run_phase.

Task run_phase within uvm_component calls another task run() which simply returns

Hence call to super.run_phase(phase) essentially calls run_phase defined in class uvm_component which doesn’t raise & drop an objection

Our test class overrides the pre_reset_phase , reset_phase and main_phase where it raises and drops an objection

As run_phase executes in parallel with sub-phases, does the sequence started in usb_agent’s run_phase continue execution till the objection is dropped in test’s main_phase ?

2

The run_phase() will execute in parallel with all of the other run-phases, so the dev_seq should run during the entire run-phase of your simulation.

The differing use of phases can lead to unpredictable behavior, especially when you bring in VIP from various sources that use phases in other ways than expected. This is why it is strongly recommended to use only the run_phase() and utilize sequences as your phasing (i.e. pre_reset_sequence, reset_sequence, main_sequence, etc.)