Back door access for uvm_mem

Hi All,

How can we add path for memory to access back-door.
There are lot of questions/information on accessing the back door register not for uvm_mem.

I’m looking a back door access of memory derived from uvm_mem.

For an example:

class my_mem extends uvm_mem;

In top reg class:

my_mem_h = my_mem :: type_id::create(“my_mem_h”);

From test I need a following:,read_data_mem,UVM_BACKDOOR);

Now uvm_mem methods to add hdl path:

// Function: add_hdl_path
// Add an HDL path
// Add the specified HDL path to the memory instance for the specified
// design abstraction. This method may be called more than once for the
// same design abstraction if the memory is physically duplicated
// in the design abstraction
extern function void add_hdl_path (uvm_hdl_path_slice slices,
string kind = “RTL”);

  1. How we can do a back-door access here?
  2. How to add a path here?

Any example would be appreciated.

In reply to Geet:

This UVM register user-defined memory backdoor - EDA Playground might be helpful
and this presentation as well Doing Funny Stuff with the UVM Register Layer: Experiences Using Front Door Sequences, Predictors, and Callbacks – DVCon Proceedings Archive



In reply to rgarcia07:


I was looking for uvm_mem. Not uvm_reg_backdoor.
Anyways, Got solution by myself by reading several methods on How to add path.

It can be done using providing path in configure method.
my_mem_h = my_mem :: type_id::create(“my_mem_h”);

Still facing below error:
UVM_ERROR /proj/eda/CADENCE/XLM/20.09.009/tools/methodology/UVM/CDNS-1.1d/sv/src/reg/uvm_reg_block.svh(2049) @ 11020.00 ns: reporter [RegModel] Block does not have hdl path defined for abstraction ‘RTL’

I’m trying to access,read_data,UVM_BACKDOOR);
Can we not read/write using read method with UVM_BACKDOOR of uvm_mem class?

If anyone has small pseudo code with uvm_mem, Please share.