Difference between put_port and get_port?

Can anyone please help me in understanding exact difference between put_port and get_port from usage and definition point of view.
Thanks

In reply to ashutosh1122:

In UVM, PORT is always an initiator of a request. It has a symbol of Square.
Export is always a provider of that request.
So put_port() method is used to send data/transaction to a consumer which has corresponding export.
Similarly, get_port() method is used to fetch some data/transaction from the consumer which has the corresponding Export (symbolizes with circle).
For more details and expample you can refer section 2.3.1.3 of UVM Verification Methodology 1.2 User’s Guide’2015.
Hope it will help you.

In reply to kapil_kumar@mentor.com:

“Absolutely helpful”!!

okies…so is it like we will be having separate physical connections for put_port and get_port?
producer | consumer
uvm_put_port #(t) put_port; | uvm_put_export #(t,consumer) put_export;
uvm_get_export #(t) get_export uvm_get_port #(t) get_port;
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In reply to ashutosh1122:

Yes We need separate connections for Port to Export.

Thanks a lot :)

I understand that put_port() is used to send a transaction to a provider and get_port() is used to retrieve a transaction from a provider. However, I’m still trying to understand the practical usage of each.

Could you please explain:

  • In what situations would we choose a put_port over a get_port?

  • Can you provide some real-world UVM/testbench examples where a component sends data using put() versus fetches data using get()?

  • From a design perspective, how do we decide whether the producer should push the data (put) or the consumer should pull the data (get)?

  • Also, someone can explain for peek.

I’m looking for the intuition behind when each mechanism is preferred.

I’d recommend to read the UVM Cookbook or attend a UVM training course.

Thank you for the suggestion. I looked through the UVM Cookbook, but I couldn’t find much theoretical explanation about when to use put(), get(), and peek() from a design or practical perspective.

I’m specifically trying to understand the intuition behind choosing one mechanism over another, along with some real-world UVM/testbench use cases.

If anyone has insights or examples, I’d really appreciate the explanation.